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DILL: Specifying Digital Logic in LOTOS (1970)

Abstract
Data Type) operations on input values. However, the time-dependent behaviour of logic circuits is often important, so it is better to use LOTOS behaviour expressions. More importantly, a specification using ADTs would not readily support `wiring up' a circuit. Each logic gate is therefore specified as a LOTOS process, instantiated with appropriate parameters. A real logic gate exhibits a propagation delay from a change in input to the subsequent output. This appears naturally in a LOTOS specification since output events follow input events. However, the actual time delay between such events is not modelled in LOTOS. For many purposes the exact delay is unimportant, since a design that assumed specific propagation delays in each real gate might be prone to race conditions. Many logic designs are synchronous to 2 Since `gate' has both a hardware meaning and a LOTOS meaning, the term is qualified where necessary. avoid such problems, and this removes the need to model delays explicitl...

Publication details
Download http://citeseer.ist.psu.edu/139676.html
Source ftp://ftp.cs.stir.ac.uk/pub/staff/kjt/research/pubs/dill.ps.gz
Publisher unknown
Contributors The Pennsylvania State University CiteSeer Archives
Repository CiteSeer (United States)
Keywords Kenneth J. Turner,Paul D. Amer,M. Umit Uyar,K. J. Turner,R. O. Sinnott DILL: Specifying Digital Logic in LOTOS
Language Englisch
Relation oai:CiteSeerPSU:249087, oai:CiteSeerPSU:209114, oai:CiteSeerPSU:368197, oai:CiteSeerPSU:368197, oai:CiteSeerPSU:67716