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Experience with a clustered parallel reduction machine (1993) |
- Beemster, M.,
- Hartel, P.H.,
- Hertzberger, L.O.,
- Hofman, R.F.H.,
- Langendoen, K.G.,
- Li, L.L.,
- Milikowski, R.,
- Vree, W.G.,
- Barendregt, H.P.,
- Mulder, J.C.
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Abstract |
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A clustered architecture has been designed to exploit divide and conquer parallelism in functional programs. The programming methodology developed for the machine is based on explicit annotations and program transformations. It has been successfully applied to a number of algorithms resulting in a benchmark of small and medium size parallel functional programs. Sophisticated compilation techniques are used such as strictness analysis on non-flat domains and RISC and VLIW code generation. Parallel jobs are distributed by an efficient hierarchical scheduler. A special processor for graph reduction has been designed as a basic block for the machine. A prototype of a single cluster machine has been constructed with stock hardware. This paper describes the experience with the project and its current state. |
Publication details |
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Cited publications (11) |
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Parallel Graph Reduction with the -machine (1995)
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The Dutch parallel reduction machine project (1987)
- Barendregt, H. P.,
- Van Eekelen, M. C. J. D.,
- Hartel, P. H.,
- Hertzberger, L. O.,
- Plasmeijer, M. J.,
- Vree, W. G.
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Experience with a Clustered Parallel Reduction Machine (1996)
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A Transformation System for Developing Recursive Programs (2001)
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Performance analysis of storage management in combinator graph reduction (1988)
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Scientific Applications on Transputer Arrays - Some Experiments in MIMD Parallelism" (1990)
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FCG: a Code Generator for Lazy Functional Languages (1996)
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Distributed Implementation of Programmed Graph Reduction (1995)
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GAML: a Parallel Implementation of Lazy ML (1995)
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Implementing lazy functional languages on stock hardware: the Spineless Tagless G-machine - Version 2.5 (1993)
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