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Theoretical and practical minimum of the power consumption of 3 ADCs in SC technique (2007)

Abstract

In this paper the theoretical and practical minimum of the power consumption is investigated for 3 ADC architectures, which are predestined for low conversion speed and applications in low-power sensor readout circuits. The analysis is made for the switched capacitor versions of the SAR ADC, cyclic ADC and sigma-delta modulator. The theoretical limit of the power efficiency is investigated by a commonly used figure of merit (FOM). As a case study two low-power ADCs fabricated in different technologies a technology-independent FOM is introduced.

Publication details

Repository	Fraunhofer Publica (Germany)
Keywords	minimum, power consumption, ADC, SC, switched capacitor, sigma-delta modulator, low-power, downscaling, figure of merit, FOM, technology independent, noise, SAR ADC, cyclic ADC, Leistungsverbrauch, zyklischer ADC, Skalierung
Type	Conference Paper
Language	english
Relation	Institute of Electrical and Electronics Engineers -IEEE-: ECCTD 2007,18th European Conference on Circuit Theory and Design: August 26-30, Sevilla, Spain. New York, NY: IEEE, 2007, pp. 444-447