| Reservation Station Architecture for Mutable Functional Unit Usage in Superscalar Processors (2008) | |||||||||||||||
Abstract | |||||||||||||||
| One major bottleneck of a superscalar processor is mismatch of instruction stream mix with functional unit configuration. Depending on the type and number of functional units, the performance loss caused by this mismatch can be significant. In this paper, we introduce mutable functional units (MFU) that enable floating point units to serve integer operations, and propose a novel architectural solution to this mismatch problem to enhance the performance of integerintensive applications while not adversely affecting the performance of floating-point-intensive applications. Modifications to a base MIPS R1000-like architecture include the MFU, an additional reservation station dedicated to the MFU, and a steering logic. We obtain a speedup ranging from 8.3 % to 14.3 % for integer application, while keeping the hardware cost resulting from the architecture modification minimal (<1 % die area). In addition, our modification does not affect clock frequency of the processor and maintains binary compatibility. 1 | |||||||||||||||
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