| An Area-Efficient GF(2 m) MSD Multiplier based on an MSB Multiplier for Elliptic Curve LSI (2008) | |||||||||||||||
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| Abstract: In this paper, we propose an MSD (most significant digit) multiplier based on an MSB (most significant bit) multiplier over GF(2 m). The proposed multiplier is based on connecting D (digit size)-bit bit-operations in series. In each digit operation in our proposed multiplier, the “left shift and reduction operation ” is serially performed for each of D bits. Because registers for storing intermediate computational results have only m bit independent of digit size of D, we can reduce register size compared to conventional digit-serial multipliers. We also implemented an ECC LSI using the proposed MSD multiplier. 1. | |||||||||||||||
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