| Multicommodity Flow Algorithms for Buffered Global Routing (2008) | |||||||||||||||
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| Due to delay scaling effects in deep-submicron technologies, interconnect planning and synthesis are becoming critical to meeting chip performance targets with reduced design turnaround time. In particular, the global routing phase of the design cycle is receiving renewed interest, as it must efficiently handle increasingly more complex constraints for increasingly larger designs (see [14] for a recent survey). In addition to handling | |||||||||||||||
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