| Dalhousie University (2008) | |||||||||||||
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| Abstract One of the important factors that governs the performance of a parallel computer system is the algorithm that determines the routing of messages in the interconnection network. There have been a number of routing algorithms proposed in the literature for various interconnection networks. The objective of this paper is to present a scheme for classification of routing algorithms on direct networks. The classification scheme is based on five main categories: hardware specification, destination type, worst-case characteristics, fault-tolerance, and performance. To illustrate its use, we have applied it to several previously proposed routing algorithms. It is shown that the scheme serves as a powerful tool in comparing the performance features of routing algorithms for direct networks. The taxonomy summarizes routing techniques, showing what features it lacks, and where extension would be worthwhile. For example, we observe (by classifying it) that Algorithm A1 is an effective hypercube routing algorithm; however, its large header size causes it to perform poorly. This leads to an improvement that drastically reduces the header size. Furthermore, we see how one can combine routing algorithms to create general hybrid strategies. We thus hope that our classification scheme will facilitate research in the area of routing algorithm development. 1 Introduction The implementation of many parallel and distributed algorithms on multiprocessor systems requires intensive communications between processors 1;2;3;4. Consequently, one of the dominating factors that governs the performance of a parallel computer system is the underlying interconnection network and the associated algorithms that determine the routing of messages from one processor to another. Static interconnection networks, also known as direct networks 1, are a popular class of interconnection networks which are characterized by static links (or channels) conforming to a specific topology. Direct networks have been employed in many commercial parallel machines such as the Cray T3E, CM-5, Tera supercomputer, nCUBE, and Intel Paragon, iPSC and iWarp 1;5. | |||||||||||||
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