| Boosting the Speedup of Future Processor Architectures by Using Mutable Functional Units (1999) | |||||||||||||||
Abstract | |||||||||||||||
| One major bottleneck of a superscalar processor is the mismatch of instruction stream mix with functional unit configuration. The resulting "unavailable functional unit" stalls can be a significant factor of performance loss. Recently, mutable functional units (MFUs) - functional units that can serve both floating-point and integer operations - have been proposed to reduce this type of stall. The benefit to our implementation of an MFU is increased integer execution bandwidth without increased die area or power consumption. In this paper, we show that the ILP gain, as well as the speedup, provided by the MFU increases in many architecture modifications expected in the future. The speedup ranges from 8% to 22%. We conclude that MFUs show promise in improving the performance of future architectures. | |||||||||||||||
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