| A Systematic Approach to Optimizing and Verifying Synthesized High-Speed ASICs (1995) | |||||||||||||||
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| This paper describes the design process used in developing a Stream Memory Controller (SMC)*. The SMC can reorder processor-memory accesses dynamically to increase the effective memory bandwidth for vector operations. A 132-pin ASIC was implemented in static CMOS using a 0.75µm process and has been tested at 36MHz. * This work was sponsored by the National Science Foundation under Grant MIP-9307626. Appeared in ASIC'95, Austin, TX, September 1995 2 also implemented using a dual ported SRAM and is used to store the base, length, and stride information for each stream. The Processor Bus Interface (PBI) state machine provides the logic necessary to interface the SMC with the i860 processor bus. The Bank Controller logic handles the interleaved memory system interface and fills or drains the FIFOs as required. The Bank Controller also provides support for scalar accesses to the SMC memory space. The FIFOs buffer data between the processor bus and the memory system bus and can be accessed... | |||||||||||||||
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