| On-Chip Optical Interconnect for Reduced Delay Uncertainty (2008) | |||||||||||||||
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| Abstract — Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become increasingly stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy a variety of design requirements. On-chip optical interconnect has been considered as a potential partial substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Based on these predictions, the delay uncertainty in electrical and optical interconnects is analyzed, and shown to affect both the latency and bandwidth of the interconnect. The two interconnects are also compared for latency, power, and bandwidth density. I. | |||||||||||||||
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