| com/archive/articles/0103ate.htm (2003) | |||||||||||||||||
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| VIII. CONCLUSION In this paper, an efficient implementation of a TAM is proposed for the MSOC testing. The technique introduces I/O access of the analog cores through the MTAM switch, which is introduced in the design. An integrated scheduling algorithm for MSOCs is proposed. The method is fully digitally compliant and, therefore, analog and digital cores can be tested in parallel. To test the algorithm, a CAT tool has been developed. A number of MSOCs have been designed using ISCAS’89 circuits for digital cores and ITC’97 circuits for analog cores. Results on these MSOCs show that the proposed method provides 100 % fault coverage and offers a hardware-efficient integrated DFT solution. | |||||||||||||||||
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