| Plasma charging damage reduction in IC processing by a self-balancing interconnect (2004) | |||||||||||||
Abstract | |||||||||||||
| In this paper, a novel first order self-balancing interconnect layout design is proposed for reducing plasma-process induced charging damage (P2ID) in modern CMOS processes. According to the mechanism of P2ID, dense interconnect lines collect positive charges due to electron shading (ES) effect [1] while sparse interconnect lines collect negative charges due to extended electron shading effect (EES) [2]. If the layout of the interconnect lines is such that the spacing between the interconnect lines is alternately wide and narrow both negative and positive charges are collected. Because these charges balance each other, the P2ID is reduced. (C) 2004 Published by Elsevier Ltd. | |||||||||||||
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