| on Security in Reconfigurable Systems Design, 2008 Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures (2009) | |||||||||||||||||
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| A novel trust-based design method for FPGA circuits that uses error-correcting code (ECC) structures for detecting design tampers—changes, deletion of existing logic, and addition of extradesign logic like Trojans—is proposed in this paper. We determine ECC-based CLB (configuration logic block) “parity groups ” and embed the check CLBs for each parity group in the FPGA circuit. During a trust-checking phase, a Test-Pattern Generator (TPG) and an Output Response Analyzer (ORA) are dynamically configured to check that each parity group of CLB outputs produce the expected parities. We use two levels of randomization to thwart attempts by an adversary to discover the parity groups and inject tampers that mask each other and/or tamper with the TPG and ORA so that design tampers remain undetected: (a) randomization of the mapping of the ECC parity groups to the CLB array; (b) randomization within each parity group of odd and even parities for different input combinations (classically, all ECC parity groups have even parities across all input combinations). These randomizations along with the error-detecting property of the underlying ECC lead to design tampers being uncovered with very high probabilities, as we show both analytically and empirically. We also classify different CLB function structures and impose a parity group selection in which only similarly-structured functions are randomly selected | |||||||||||||||||
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