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Fully Compatible Integration of High Density Embedded DRAM with 65nm CMOS Technology (CMOS5) (2009)

Y. Matsubara,
M. Habu,
S. Matsuda,
K. Honda,
E. Morifuji,
T. Yoshida,
K. Kokubun,
K. Yasumoto,
T. Sakurai,
T. Suzuki,
J. Yoshikawa,
E. Takahashi,
K. Hiyama,
R. Ishizuka,
M. Moriuchi,
H. Koga,
Y. Fukuzaki,
Y. Sogo,
H. Takahashi,
N. Nagashima,
Y. Okamoto,
S. Yamada,
T. Noguchi

Abstract

65nm node SoC technology has been achieved to show good yield of 8M bit DRAM ADM using tapered BF2 implantation without additional mask step, which cell size is 0.11um 2 [1], with 3 layers hybrid low-k material, SiLK/BD/BLOk, and Cu integration.

Publication details

Download	http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.143.8298
Source	http://www.ece.umd.edu/courses/enee759h.S2005/references/0423mats.pdf
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Repository	CiteSeerX - Scientific Literature Digital Library and Search Engine (United States)
Type	text
Language	English