| A Novel Low-Power Logic Circuit Design Scheme (2009) | |||||||||||||||
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| Abstract—This brief proposes a novel low-power digital logic design scheme based on the energy exchange in the switched inductor–capacitor (SLC) circuit. It presents a design paradigm which in ideal case may lead to a circuit capable of performing logic operations with no switching losses. In traditional integrated circuit design, the energy is stored in the output load capacitor through a pull-up path (corresponding to storing a logic 1). When the output changes its logic value, this stored energy is dissipated through the pull down path to the ground. In order to reduce this switching energy dissipation each time the load capacitor is discharged, we store its energy in the magnetic field of the inductor in the proposed SLC architecture. Whenever the output load needs to be charged again, we transfer the energy back from the inductor to the load capacitor. This significantly reduces the switching energy. We illustrated the operation of the SLC architecture through SPICE simulation. A brief discussion of some practical considerations for this architecture is also presented. Index Terms—Buses, clock distribution tree, logic design, low power, switched inductor–capacitor (SLC) circuit. I. | |||||||||||||||
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