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A new gate process for the realization of lattice - matched HEMT on InP for high yield MMICs (1998)

Abstract

A new gate process for the realization of ultra short gate HEMT on InP is presented. In this technology, the top of the gate is deposited on a Si3N4 layer. This gate process leads to small footprints, mechanically strong devices and good yield. Using this gate technology, HEMT with high Ft were realized and characterized. The influence of the Si3N4 removing was also investigated.

Publication details

Download	http://amsacta.cib.unibo.it/archive/00001667/
Repository	AMS Acta (Italy)
Keywords	ING-INF/01 Elettronica
Type	Documento relativo ad un convegno o altro evento
Relation	http://amsacta.cib.unibo.it/archive/00001667/01/GAAS_98_123.pdf [1] « 60- and 77- GHz monolithic amplifiers utilizing InP-based HEMTs and coplanar waveguides » ; M. Berg, J. Dickmann, R. Guehl, W. Bischof, Microwave and optical technology letters, Vol. 11, No.3, p. 139-145 , February 20 1996. [2] « A super low noise AlInAs/InGaAs HEMT processed by selective wet gate recess etching » ; N. Yoshida, T.Kitano, Y. Yamamoto, and S. Mitsui, IEEE transactions on electronic devices, Vol. 43, No.l, p. 178-180, January 1996. [3] « A 155-GHz Monolithic InP-Based HEMT Amplifier* ; H. Wang, R. Lai, Y.C. Chen and B. Allen, p. 1275-1278, 1997 IEEE MTT-S Digest.