Tools And Library, Amaury Darsch, Pierre Villalon, Andre Seznec, I Isa Library
this memory logic reset this memlogic . void bind (Memory #mem) . void update (Result &resl) The MemLogic(p. 53) class is a class that handle the interferences between the memory and the alat....
Speculative Return Address Stack management revisited (2008)
Vandierendonck, Hans, Seznec, Andre
Branch prediction feeds a speculative execution processor core with instructions. Branch mispredictions are inevitable and have negative effects on performance and energy consumption. With the advent...
Don't Use the Page Number, But a Pointer on It (2007)
: Most newly announced microprocessors manipulate 64-bit virtual addresses and the width of physical addresses is also growing. As a result, the relative size of the address tags in the L1 cache is...
Performance Implications of Single Thread Migration on a Chip Multi-Core (2005)
Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, Andre Seznec
High performance multi-core processors are becoming an industry reality. Although multi-cores are suited for multithreaded and multi-programmed workloads, many applications are still mono-thread and...
Performance Implications of Single Thread Migration on a Chip Multi-Core (2005)
Theofanis Constantinou, Yiannakis Sazeides, Pierre Michaud, Damien Fetis, Andre Seznec
High performance multi-core processors are becoming an industry reality. Although multi-cores are suited for multithreaded and multi-programmed workloads, many applications are still mono-thread and...
Iato Ia Toolkit, Amaury Darsch, Pierre Villalon, Andre Seznec, Getting Started
Contents 1 Getting started 1 1.1 Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 Supported platforms . . . . . . . . . . . . . . . . . . . . . . 2 1.1.2 IA64 binary...
Speculative Software Management of Datapath-width for Energy Optimization (2004)
Gilles Pokam, Andre Seznec, Olivier Rochecouste, Francois Bodin
This paper evaluates managing the processor's datapathwidth at the compiler level by means of exploiting dynamic narrow-width operands. We capitalize on the large occurrence of these operands in...
Design tradeoffs for the alpha EV8 conditional branch predictor (2002)
Andre Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides
This paper presents the Alpha EV8 conditional branch predictor. The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressive 8-wide issue...
Data-flow Prescheduling for Large Instruction Windows in Out-of-Order Processors (2001)
The performance of out-of-order processors increases with the instruction window size. In conventional processors, the effective instruction window cannot be larger than the issue buffer. Determining...
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors (1999)
Pierre Michaud Irisa, Pierre Michaud, Andre Seznec, Stephan Jourdan
The effective performance of wide-issue superscalar processors depends on many parameters, such as branch prediction accuracy, available instruction-level parallelism, and instruction-fetch...
Trading conflict and capacity aliasing in conditional branch predictors (1997)
Pierre Michaud, Andre Seznec, Richard Uhlig
As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on accurate branch prediction. Because hardware resources for...
A Synchronous Approach for Hardware Design (1997)
Michel Allemand, Francois Bodin, Apostolos Kountouris, Fran Cois Bodin, Paul Le Guernic, Andre Seznec, ...
: In this report we present a methodology for designing complex hardware systems. This methodology is based on the synchronous data flow language Signal which offers a formal framework to build...
Salto: System for assembly-language transformation and optimization (1996)
Apport De Recherche, François Bodin, André Seznec, François Charot, Frédéric Raimbault, Erven Rohou, ...
On critical applications, particularly embedded systems, the performance tuning requires multiple passes. Salto #System for Assembly Language Transformation and Optimization# is a retargetable...
Interleaved Sectored Caches: reconciling low tag volume and low miss ratio (1993)
: Sectored caches have been used for many years in order to reduce the tag volume needed in a cache. In a sectored cache, a single address tag is associated with a sector consisting in several cache...