Design for Verification in System-level Models and RTL (2008)
Anmol Mathur, Venkat Krishnaswamy
It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often the case that by...
Plot Nos.57 A&B, Noida Export Processing Zone (2008)
Mangalam G. N, Sanjiv Narayan, Paul Van Besouw, Lanae Avra, Anmol Mathur, Sanjeev Saluja
Abstract- Tree height reduction helps in minimizing the critical path delay and area in datapath rich designs during synthesis. We introduce in this paper, the necessary condi-tions to identify...
RATAN:Atool for rate analysis and rate constraint debugging for embedded systems (2008)
Ali Dasdan, Anmol Mathur, Rajesh K. Gupta
The increasingly complex design of embedded systems creates the problems of specifying consistent and satis able rate constraints on process execution rates, checking them for consistency and satis...
RATAN:Atool for rate analysis and rate constraint debugging for embedded systems (2007)
Ali Dasdan, Anmol Mathur, Rajesh K. Gupta
dasdan�cs.uiuc.edu anmol�mti.sgi.com rgupta�ics.uci.edu The increasingly complex design of embedded sys� tems creates the problems of specifying consistent and satis�able rate constraints...
An E cient Assertion Checker for Combinational Properties (2007)
Gagan Hasteer Y, Anmol Mathur, Prithviraj Banerjee
Formally verifying properties of signals in a circuit has several applications in an equivalence checking based formal veri cation ow. In a hierarchical design, functionality is divided across...
Embedded tutorial: Formal equivalence checking between system-level models and RTL (2005)
Alfred Koelbl, Yuan Lu, Anmol Mathur
0-7803-9254-X/05/$20.00 ©2005 IEEE. 965 1
An implicit algorithm for finding steady states and its applications to FSM verifcation (1998)
Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
Finding the set of steady states of a machine has applications in formal veri cation, sequential synthesis and ATPG. Existing techniques assume the presence of a designated set of initial states...
Efficient Equivalence Checking of Multi-Phase Designs Using Retiming (1998)
Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
The use of multi-phase clocking scheme, aggressive pipelining and #sparse" encodings in high performance designs results in a tremendous increase in the state space. In this paper, we show that...
Rate Analysis for Embedded Systems (1998)
Anmol Mathur, Ali Dasdan, Rajesh K. Gupta
ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission...
An implicit algorithm for finding steady states and its applications to FSM verifcation (1998)
Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
Finding the set of steady states of a machine has applications in formal veri cation, sequential synthesis and ATPG. Existing techniques assume the presence of a designated set of initial states...
Rate analysis of embedded systems (1998)
Anmol Mathur, Ali Dasdan, Rajesh K. Gupta
Abstract. Embedded systems consist of interacting components that are required to deliver a speci c functionality under constraints on execution rates and relative timing of the components. In this...
RATAN: A Tool for Rate Analysis and Rate Constraint Debugging for Embedded Systems (1997)
Ali Dasdan, Anmol Mathur, Rajesh K. Gupta
The increasingly complex design of embedded systems creates the problems of specifying consistent and satisfiable rate constraints on process execution rates, checking them for consistency and...
RATAN: A Tool for Rate Analysis and Rate Constraint Debugging for Embedded Systems (1997)
Ali Dasdan, Anmol Mathur, Rajesh K. Gupta
The increasingly complex design of embedded systems creates the problems of specifying consistent and satisfiable rate constraints on process execution rates, checking them for consistency and...
Rate Analysis for Embedded Systems (1996)
Anmol Mathur, Ali Dasdan, Rajesh K. Gupta
. Embedded systems consist of interacting components that are required to deliver a specific functionality under constraints on execution rates and relative timing of the components. In this paper we...