A scheme for multiple on-chip signature checking for embedded SRAMS (2000)
Abdulla, M F, Ravikumar, C P, Kumar, Anshul
Embedded read/write memories are integral parts of many VLSI chips designed for specific applications in the areas of computer communications, multimedia, and digital signal processing. Testing an...
Testing interconnects in a system chip (2000)
Testing of interconnects on a printed circuit board has been studied and the procedure has been standardized in the IEEE 1149.1 (JTAG) standard. The system-on-chip (SOC) technology allows us to...
Ravikumar, C P, Chandra, G, Verma, A
We address the problem of power-constrained testing of core based system chips. Built-in self-test methodology for testing individual cores is assumed, and sharing of test resources (pattern...
Power Estimation from Hierarchical Netlists (1999)
C. P. Ravikumar, Mukul R. Prasad
We describe a power estimation tool that works at the register-transfer level of abstraction. Such a tool is useful when a transformational based approach is employed to minimize the energy and/or...
Efficient Algorithms for Delay-bounded Minimum Cost Path Problem in Communication Networks (1999)
Girish Kumar, Nishit Narang, C. P. Ravikumar
As the amount of data transmitted over a network increases and high bandwidth applications requiring point to multipoint communications like videoconferencing, distributed database management of...
Distributed Delay Constrained Multicast Path Setup Algorithm For High Speed Networks (1999)
Ramnik Bajaj, C. P. Ravikumar, Suresh Chandra
The problem of finding an optimal multicast tree in a point to point network translates to the Steiner Problem in graphs. Since the Steiner problem is NPcomplete, heuristic approaches are required...
Call Admission Control and Routing in ATM Networks for Multimedia Communications (1999)
Wide area ATM networks increasingly carry multimedia traffic due to the popularity of the World Wide Web, Video-on-demand, Distance Education, and Video Conferencing. In this paper, we are concerned...
A functional-level testability measure for register-level circuits and its estimation (1999)
Ravikumar, C P, Saund, G S, Agrawal, N
Estimation of circuit testability is an important issue when evaluating the circuit design. A testability measure indicates how easy or difficult it would be to generate tests for the circuit. STAFAN...
A polynomial-time algorithm for power constrained testing of core based systems (1999)
Ravikumar, C P, Verma, A, Chandra, G
We address the problem of scheduling test sessions for core based systems-on-chip (SOC). We assume the built-in self-test methodology for testing individual cores and permit sharing of test resources...
Hierarchical delay fault simulation (1999)
Increasingly, VLSI systems are being designed using macro blocks and predesigned cores. Since the clock rate at which these circuits operate is steadily increasing, it is important to perform delay...
Improving the diagnosability of digital circuits (1999)
Ravikumar, C P, Sharma, M, Patney, R K
Testing and fault diagnosis of core-based systems are both difficult problems. Being able to identify which module in the core-based system is faulty has become very important. In this paper, we...
Source-based delay-bounded multicasting in multimedia (1998)
Ravikumar, C P, Bajpai, Rajneesh
In multimedia communication networks, the problem of multicasting assumes a new dimension. Apart from minimizing the cost of multicast communication, it is also necessary to ensure that each of the...
Performance-driven design and redesign of high-speed local area networks (1998)
Ravikumar, C P, Pandit, D R, Mishra, A
Although distributed computing over a network of computers has become a reality, its success mainly depends on the performance of the underlying network. In this paper, we consider the problem of...
Evaluating BIST architectures for low power (1998)
The "system-on-chip" revolution has posed a number of new challenges to the test engineers. We address the issue of high power dissipation during testing, which can reach levels that are beyond the...
Hybrid testing schemes based on mutual and signature testing (1998)
Abdulla, M F, Ravikumar, C P, A Kumar
Signature based techniques have been well known for the built-in self-test of integrated systems. We propose a novel test architecture which uses a judicious combination of mutual testing and...
Synthesis of testable RTL designs (1998)
Ravikumar, C P, Gupta, S, Jajoo, A
With several commercial tools becoming available, the high-level synthesis of application-specific integrated circuits is finding wide spread acceptance in VLSI industry today. Existing tools for...
On-chip signature checking for embedded memories (1998)
Abdulla, M F, Ravikumar, C P, A Kumar
The multiple on-chip signature checking architecture proposed by the authors previously is an effective BIST architecture for testing the functional units in modern VLSI circuits. It is characterized...
Synthesis of Testable RTL Designs using Adaptive Simulated Annealing Algorithm (1997)
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
With several commercial tools becoming available, the high-level synthesis of applicationspecific integrated circuits is finding wide spread acceptance in VLSI industry today. Existing tools for...
Distributed Delay Constrained Multicast Path Setup Algorithm For High Speed Networks (1997)
Ramnik Bajaj, C. P. Ravikumar, Suresh Chandra
The problem of finding an optimal multicast tree in a point to point network translates to the Steiner Problem in graphs. Since the Steiner problem is NPcomplete, heuristic approaches are required...
Hierarchical Delay Test Generation (1997)
Ravikumar, C.P., Agrawal, Nitin, Agarwal, Parul
Delay testing is used to detect timing errors in a digital circuit.In this paper, we report a tool called MODET forautomatic test generation for path delay faults in modular combinational circuits....
Adaptive routing in k-ary n-cubes using incomplete diagnostic information (1997)
In this paper, we present a fault-tolerant routing algorithm for k-ary n-cube interconnection networks which have become increasingly popular for the construction of massively parallel computers. The...
Parallelization of symmetry detection algorithms on a network of workstations (1997)
Parthiban, R, Ravikumar, C P, Kakarala, R, Sivaswamy, J
Detection of spatial symmetry is useful in several computer vision applications. Due to the real-time nature of the applications, it is important that symmetry detection algorithms be computationally...
A scheme for multiple on-chip signature checking for embedded SRAMs (1997)
Abdulla, M F, Ravikumar, C P, A Kumar
Pseudorandom self testing of embedded memories is commonly used because of its simplicity. A novel scheme pseudorandom testing with multiple on-chip signature checking (MOSC) has been proposed....
Efficient implementation of multiple on-chip signature checking (1997)
Abdulla, M F, Ravikumar, C P, A Kumar
Detection latency in a BIST scheme is the delay between the time instant at which a faulty response appears and the time instant at which the fault is detected. Conventional BILBO-BIST schemes suffer...
Faster fault simulation through distributed computing (1997)
Ravikumar, C P, Jain, V, Dod, A
n this paper, we describe distributed algorithms for combinational fault simulation assuming the classical stuck-at fault model. Our algorithms have been implemented on a network of Sun workstations...
A graph-theoretic approach for register file based synthesis (1997)
Ravikumar, C P, Aggarwal, R, Sharma, C
With the increasing use of register files as storage elements in integrated circuits, the problem of assigning data variables to ports of register files has assumed significance. The assignment...
An Euler path based technique for deadlock-free multicasting (1997)
The existing algorithms for deadlock-free multicasting in interconnection networks assume the Hamiltonian property in the networks topology. However, these networks fail to be Hamiltonian in the...
Fault-tolerant routing in multiply twisted cube topology (1996)
In an attempt to improve the communication diameter of the hypercube interconnection network,variations of the hypercube topology called the twisted cubes have been proposed in the literature.among...
Efficient delay test generation for modular circuits (1996)
Ravikumar, C P, Agrawal, N, Agarwal, P
In this paper, we report a tool called MODET for automatic test generation for path delay faults in modular combinational circuits. Our technique uses precomputed robust delay tests for individual...
Genetic algorithms for scan path design (1996)
In this paper, we consider genetic algorithms for two problems connected with scan path design for VLSI circuits. The first problem, called partial scan path selection, is to optimize the number of...
A novel BIST architecture with built-in self check (1996)
Abdulla, M F, Ravikumar, C P, A Kumar
We propose an improved BIST architecture which supports on-chip comparison of signatures at no significant increase in area. The BILBO-based BIST architecture, used popularly in application-specific...
Synthesis of testable pipelined datapaths using genetic search (1996)
In this paper, we describe TOGAPS, a Testability-Oriented Genetic Algorithm for Pipeline Synthesis. The input to TOGAPS is an unscheduled data flow graph along with a specification of the desired...
Estimation of power from module-level netlists (1996)
Ravikumar, C P, Prasad, M R, Hora, L S
Existing power estimation tools work on gate-level netlists and cannot be readily adapted for module-level circuits. Flattening the module-level netlist to gate level for purposes of power estimation...
A genetic algorithm for assembling optical computers using faulty optical arrays (1996)
Ravikumar, C P, Thomas, A R, Gupta, A
A digital optical computer architecture consists of several stages, or slots, of optical arrays. Each slot can be viewed as a rectangular array of locations which are classified as vital and...
Heuristic and Neural Algorithms for Mapping Tasks to a Reconfigurable Array (1995)
We consider the problem of mapping tasks onto processors in a reconfigurable array architecture. We assume a directed acyclic task graph as input. The node weights in the task graph represent their...
Deadlock-free wormhole routing algorithms for star graph topology (1995)
For constructing massively parallel multicomputers with over 5000 processing nodes, the star graph topology is known to be better than the hypercube in terms of the average routing distance, the...
HISCOAP: a hierarchical testability analysis tool (1995)
We describe a time and space efficient technique for evaluating the SCOAP testability measure of a circuit from its hierarchical description. Under the stuck at fault model, the SCOAP measure...
A STAFAN-like functional testability measure for register-level circuits (1995)
Ravikumar, C P, Saund, G S, Agrawal, N
STAFAN (statistical fault analysis) is a well known testability analysis program which predicts the fault coverage of a digital circuit under the stuck-at fault model, without actually performing...
Simulated annealing for target-oriented partial scan (1994)
In this paper, we describe algorithms based on simulated annealing for selecting a subset of flip-flops to be connected into a scan path. The objective for selection is to maximise the coverage of...
Star-Graph based multistage interconnection network for ATM switch fabric (1994)
This paper considers a multistage interconnection network based on the Indirect Star Graph topology as a candidate for an ATM (Asynchronous Transfer Mode) switch fabric. We consider both buffered and...
Parallel search-and-learn technique for solving large scale travelling-salesperson problems (1994)
Parallel processing has traditionally been used to achieve higher speed while solving computational problems of large size. The greater availability of parallel and distributed computing opens yet...
A parallel search-and-learn technique for solving large scale TSP (1993)
Describes a parallel search-and-learn technique for obtaining high quality solutions to the traveling salesperson problem (TSP). The combinatorial search space is decomposed so that multiple...
Solving physical design problems on a vector machine (1992)
In this paper, discribe parallel algorithms for two physical design problems.The target machine is the Alliant FX/80, which is shared memory multiprocessor with up to 8 advanced computational...
Interval partition with bounded overlap (1992)
The paper considers an optimization technique with applications to some resource-allocation problems that arise in high-level synthesis of digital systems. In an abstract sense, the optimization...
Parallel techniques for solving large scale travelling salesperson problems (1992)
As a hard combinatorial optimization problem, the travelling salesperson problem (TSP) has been of pedagogical interest for more than 50 years. More recently, the problem has generated a great deal...
Distributed Delay Constrained Multicast Path Setup Algorithm For High Speed Networks (1970)
Ramnik Bajaj, C. P. Ravikumar, Suresh Chandra
The problem of finding an optimal multicast tree in a point to point network translates to the Steiner Problem in graphs. Since the Steiner problem is NPcomplete, heuristic approaches are required...