Pulsed behavior of polymer protection devices (2009)
Bonfert, D., Gieser, H., Bock, K., Svasta, P., Ionescu, C.
Polymer protection devices are placed on circuit boards as chip devices to protect existing electronic devices from electrostatic discharge events (ESD). As there are no generally accepted standards...
Pulsed stress behavior of flexible thick film resistors (2008)
Bonfert, D., Wolf, H., Gieser, H., Klink, G., Bock, K., Svasta, P., ...
In order to investigate the behavior for very high current densities on polymer resistors on flexible substrates, a pulsed measurement technique was applied. The analytical test technique of...
Transmission line pulse stress on thick film resistors (2007)
Bonfert, D., Wolf, H., Gieser, H., Svasta, P., Romanescu, A., Cazacu, E.
One of the most important issues of resistors properties is the value stability under different electrical and non electrical influences. Mechanical and/or thermal stress together with the electrical...
ESD susceptibility of submicron air gaps (2006)
Wolf, H., Gieser, H., Bonfert, D., Hauser, M.
This work describes the investigation of the ESD susceptibility of submicron air gaps which are used e.g. in filter devices. The breakdown behaviour of the air gaps is analyzed in both the HBM (Human...
Transient-induced latch-up test setup for wafer-level and package-level (2006)
Bonfert, D., Gieser, H., Wolf, H., Frank, M., Konrad, A., Schulz, J.
Latch-up triggered by an impulse of short duration, is one root cause for field failures of CMOS devices. Standard tests. like JEDEC 78, which apply quasi-static overvoltage and overcurrent may fail...
ESD susceptibility of thick film chip resistors by means of transmission line pulsing (2006)
Bonfert, D., Wolf, H., Gieser, H., Stocker, A.
The change in resistance (dR) due to an applied high voltage pulse is a measure of the electrostatic discharge susceptibility of a resistor. The influence of the pulse width and height on the...
3D integration of CMOS transistors with ICV-SLID technology (2005)
Wieland, R., Bonfert, D., Klumpp, A., Merkel, R., Nebrich, L., Weber, J., ...
3D Integration of CMOS transistors with ICV-SLID technology is reported in this paper. NMOS and PMOS metal gate transistor devices have been further processed by forming deep trench inter-chip-vias...
High quality strained Si/SiGe substrates for CMOS and optical devices (2005)
Weber, J., Nebrich, L., Bensch, F., Neumeier, K., Vogg, G., Wieland, R., ...
InterChip via technology by using copper for vertical system integration (2002)
Ramm, P., Bonfert, D., Ecke, R., Iberl, F., Klumpp, A., Riedel, S., ...
Interchip Via Technology for Vertical System Integration (2001)
Ramm, P., Bonfert, D., Gieser, H., Haufe, J., Iberl, F., Klumpp, A., ...
Vertical System Integration(r) means the realization of three-dimensional integrated systems by thinning, stacking and vertical interchip wiring of completely processed and electrically tested device...
Transient induced latch-up triggered by very fast pulses (1999)
The sensitivity of devices to latch-up triggered by short duration pulses is an often overlooked root cause for severe field failures. Standard JEDEC 17 tests applying quasi-static voltages and...
Reliability investigations of thin film metallizations on AlN-ceramics (1990)
Bonfert, D., Drost, A., Feil, M.
AlN-Ceramic is very suitable as carrier substrate for multichip modules because of its high thermal conductivity and its coefficient of thermal expansion, which is closely matched to that of Si....