Towards Robust Data Storage in Wireless Sensor Networks (2009)
Siegmund, N, Rosenmuller, M, Moritz, G, Saake, G, Timmermann, D
Exploiting Malicious Node Detection for Lifetime Extension of Sensor Networks (2009)
R. Behnke, J. Salzmann, D. Lieckfeldt, K. Thurow, F. Golatowski, D. Timmermann
Abstract—Wireless Sensor Networks (WSN) have attracted considerable research effort in the community during the past couple of years. One of the most challenging issues so far is the extension of...
Nonuniform sampling driver design for optimal ADC utilization (2008)
F. Papenfuß, Y. Artyukh, E. Boole, D. Timmermann
Deliberate nonuniform sampling promises increased equivalent sampling rates with reduced overall hardware costs of the DSP system. The equivalent sampling rate is the sampling rate that a uniform...
H. Hahn, D. Timmermann, B. J. Hosticka, B. Rix
One of the main problems of the CORDIC algorithm is the limited convergence domain, in which the functions can be calculated. Two different approaches can be employed to overcome this constraint:...
DYNAMIC SELF-TIMED LOGIC STRUCTURES (2007)
Abstract. The realization of fast datapaths in signal processing environments requires fastest logic styles with synchronous behavior. This paper presents a systematic method which efficiently...
F. Papenfuß, Y. Artyukh, E. Boole, D. Timmermann
In some applications the observed samples are inherently nonuniform. In contrast to that in this paper we take advantage of deliberate nonuniform sampling and perform DSP where the classical...
A. Wassatsch, M. Haase, D. Timmermann
hierarchical synthesis, rapid prototyping In this application report we describe the development process of a new concept for implementing artificial neural networks. Based on the idea to utilize a...
Power Reduction In Pipeline Designs (2007)
Grassert Sill Timmermann, F. Grassert, F. Sill, D. Timmermann
The realization of fast datapaths in signal processing environments requires fastest logic styles with synchronous behavior. This paper presents a systematic method which efficiently combines...
Simulation of Mobile Wireless Networks with Accurate Modelling of Non-linear Battery Effects (2003)
For the simulation of protocols and algorithms of mobile devices, an ideal energy source, i.e. a battery with linear charge and discharge characteristics, is often assumed. However, real batteries...
Low energy adaptive clustering hierarchy with deterministic cluster-head selection (2002)
Abstract- This paper focuses on reducing the power consumption of wireless microsensor networks. Therefore, a communication protocol named LEACH (Low-Energy Adaptive Clustering Hierarchy) is...
A design flow for 12.8 gbit/s triple des using dynamic logic and standard synthesis tools (2001)
S. Flügel, F. Grassert, M. Grothmann, M. Haase, P. Nimsch, H. Ploog, ...
In this paper, we propose a 12.8Gbit/s Triple DES processor using 0.6um/5V AMS. A conventional static CMOS implementation cannot fulfill the requirements of high throughput digital designs. In...
Dynamic Single Phase Logic with Self-timed Stages for Power Reduction (2001)
True single phase clock logic techniques, e.g. with alternating arranged N- and P-logic cells, yield easy to design circuits with standard cells and high speed potential. The disadvantages are a...
An efficient implementation of modular exponentiation, i.e., the main building block of many public key cryptographic devices, is achieved by algorithmic optimization of the Montgomery modular...
Schaltungsanordnung und Verfahren zur Durchfuehrung des CORDIC-Algorithmus (1995)
Timmermann, D., Hahn, H., Hosticka, B.
A circuit arrangement of the implementation of the CORDIC algorithm for the iterative calculation of the x, y and z values at a data word length of n bits comprises the following: A first device (X)...
Hahn, H., Timmermann, D., Hosticka, B.J., Rix, B.
One of the main problems of the CORDIC algorithm is the limited convergence domain, in which the functions can be calculated. Two different approaches can be employed to overcome this constraint:...
A CMOS floating-point vector-arithmetic unit (1994)
Timmermann, D., Rix, B., Hahn, H., Hosticka, B.J.
This work describes a floating-point arithmetic unit based on the CORDIC algorithm. The unit computes a full set of high level arithmetic and elementary functions: multiplication, division, (co)sine,...
Overflow effects in redundant binary number systems (1993)
Hosticka, B.J., Timmermann, D.
This work describes a specific overflow behaviour encountered when working with redundant binary numbers, possibly yielding wrong results. This peculiarity is not encountered in conventional number...
Gleitkomma-Prozessor für rechenintensive Echtzeitanwendungen (1993)
Timmermann, D., Rix, B., Hosticka, B.J.
Zur Lösung rechenintensiver Aufgaben, z.B. in der Signalverarbeitung, wurde ein arithmetischer Prozessor entwickelt, der herkömmliche Signalprozessoren und Risc-Mikroprozessoren an Leistung weit...
24 Bit CMOS Gleitkomma Vektorarithmetik Chip (1993)
Hahn, H., Hosticka, B.J., Rix, B., Timmermann, D.
Es wird eine CMOS Realisierung einer Vektorarithmetikeinheit zur Verarbeitung von Zahlen im IEEE-754 Gleitkommaformat (24 Bit Mantisse, 8 Bit Exponent) vorgestellt, der IMSCOR24. Dieser Chip wurde...
A low latency time CORDIC algorithm with increased parallelism (1992)
Hahn, H., Hosticka, B.J., Timmermann, D.
In this contribution we present several methods for increasing the speed of the CORDIC algorithm. First we develop an improved method which guarantees a constant scale factor when employing redundant...
Cordic processor architectures (1992)
Böhme, J.F., Hahn, H., Hosticka, B.J., Timmermann, D.
As CORDIC algorithms receive more and more attention in elementary function evaluation and signal processing applications, the problem of their VLSI realization has attracted considerable interest....
A CORDIC-based floating point arithmetic unit (1992)
Hahn, H., Hosticka, B.J., Rix, B., Timmermann, D.
A floating-point arithmetic unit based on the CORDIC algorithm is described. It computes a wide range of arithmetic, trigonometric, and hyperbolic functions and achieves a normalized peak performance...
Area and latency efficient CORDIC architectures (1992)
The CORDIC algorithms has proved to be a powerful and flexible generic architecture to implement many signal processing and image processing algorithms. In practice, however, it sometimes suffers...
Hahn, H., Hosticka, B.J., Timmermann, D.
In adaptive digital signal processing, fast multiplication is one of the most important operations and is implemented as an array multiplier in a standard signal processor. For the realisation of...
Alternative DPCM architecture for high sampling rates (1992)
It is shown that by using carry save arithmetic in DPCM coders the degree of parallelization can be increased. This results in a reduced delay inside the critical recursive loop. The architecture...
A programmable CORDIC chip for digital signal processing applications (1991)
Schmidt, G., Hahn, H., Hosticka, B.J., Timmermann, D.
A chip implementing the COordinate Rotation DIgital Computer (CORDIC) algorithm is described. It contains a 10-MHz 16-b fixed-point CORDIC arithmetic unit, 2-kb RAM, a controller, and I/O registers....
A new addition scheme and fast scaling factor compensation methods for CORDIC algorithms (1991)
Hahn, H., Hosticka, B.J., Rix, B., Timmermann, D.
As CORDIC algorithms attract more and more attention in elementary function evaluation and signal processing applications, the problem of their VLSI realization has drawn considerable interest. In...
A low latency time CORDIC algorithm with increased parallelism (1991)
Hahn, H., Hosticka, B.J., Timmermann, D.
In this contribution we present several methods for increasing the speed of the CORDIC algorithm. First we develop an improved method which guarantees a constant scale factor when employing redundant...
Hardware-Algorithmen und Architekturen für die arithmetikintensive Signalverarbeitung (1991)
Hahn, H., Hosticka, B.J., Rix, B., Timmermann, D.
Diskutiert wird die Möglichkeit, aufwendige arithmetische Berechnungen direkt als Hardware-Algorithmus zu realisieren. Nach einem Vergleich der dazu zur Verfügung stehenden Alternativen zeigt sich...
Eine vollparallele CORDIC Gleitkomma Pipeline Architektur (1990)
Hahn, H., Rix, B., Timmermann, D.
In dem Forschungsvorhaben werden Architekturen für Prozessoren entwickelt, die das CORDIC Verfahren als Hardwarealgorithmus abbilden. Als konsequente Weiterentwicklung des von uns realisierten...
Modified CORDIC algorithm with reduced iterations (1989)
Hahn, H., Hosticka, B.J., Timmermann, D.
In this contribution we present a modified CORDIC algorithm that offers a considerable latency time reduction and chip area savings when compared with the original CORDIC method. The operations used...
Integrierte CORDIC-Prozessoren, Architekturen und Hardware (1989)
Hahn, H., Hosticka, B.J., Timmermann, D., Zimmer, G.
Monolithic A/D and D/A converters suffer from the limited accuracy of the available circuit components. A new self-calibration method allows the correction of the linearity errors of binary weighted...
Hough transform using cordic methods (1989)
Hahn, H., Hosticka, B.J., Timmermann, D.
The purpose of the letter is to demonstrate the usefulness of the CORDIC algorithm for implementation of image processing algorithms in dedicated hardware to achieve near real-time processing speed....
Cordic-Prozessoren für die digitale Signalverarbeitung (1989)
Eßer, W., Hahn, H., Hosticka, B.J., Schmidt, G., Timmermann, D.
Die digitale Signalverarbeitung gewinnt unter anderem durch das Angebot an Signalprozessoren, Koprozessoren und anwendungsspezifischen Einchip-Implementierungen in fortschrittlichen...
CMOS-implementation of optimized 16-bit cordic-processors and evaluation tools (1989)
Schmidt, G., Hahn, H., Hosticka, B.J., Timmermann, D., Zimmer, G., Böhme, J.F.
This paper is devoted to recursive CORDIC processors with 16 bit fixed-point arithmetics. After the presentation of unified and specialized CORDIC sequences which result from a parameter optimization...
Design of 16-Bit fixed point recursive CORDIC processors and evaluation tools (1988)
Schmidt, G., Timmermann, D., Hahn, H., Böhme, J.F., Zimmer, G.
The CORDIC algorithm calculates a set of elementary functions which include trigonometric, hyperbolic and their inverse functions as well as multiplications and divisions. We report on the parameter...
Special computers - graphics robotics (1987)
Yang, B., Böhme, J.F., Schmidt, G., Hahn, H., Hosticka, B.J., Timmermann, D., ...
This paper describes a special processor based on the CORDIC algorithm, which can perform a variety of trigonometric, hyperbolic and square-root functions as well as multiplications and divisions....
Parameter optimization of CORDIC-algorithm and implementation in a CMOS-chip (1986)
Schmidt, G., Böhme, J.F., Hahn, H., Hosticka, B.J., Timmermann, D., Zimmer, G.
CORDIC-Coprozessor für schnelle 3D-Grafik (1986)
Böhme, J.F., Schmidt, G., Hahn, H., Hosticka, B.J., Timmermann, D., Zimmer, G.
In diesem Beitrag wird ein auf der Basis des CORDIC Verfahrens arbeitender prozessor vorgestellt, der sich besonders fuer die digitale Signalverarbeitung eignet. Als ein Beispiel fuer die...
Grundsätzliche Überlegungen zur Theorie der industriellen Unternehmung / (1974)
Proefschrift T.U. Berlin.