A Parametric Study of Scalable Interconnects on FPGAs (2008)
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano
Abstract — With the constantly increasing gate capacity of FP-GAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, Network-On-Chip...
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs (2007)
WANG, Daihan, MATSUTANI, Hiroki, KOIBUCHI, Michihiro, AMANO, Hideharu
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware...