Greg Semeraro, David Albonesi, Steven Dropsho, Grigorios Magklis, Michael L. Scott
Microprocessors are traditionally designed to provide “best overall ” performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques...
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Eby G. Friedman, David Albonesi
Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the...
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Eby G. Friedman, David Albonesi
Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the...
Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, Hya Dwarkadas
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that leverages repeater...
Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Peter Cook, David Albonesi
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a...
A Dynamic Reconfigurable Clock Generator (2007)
Radu M. Secareanu, David Albonesi, Eby C. Friedman
Abstract--A circuit to dynamically reconfigure the clock frequency of a synchronous digital system according to the changing needs of the application is described in this paper. The circuit changes...
A DYNAMIC RECONFIGURABLE CLOCK GENERATOR (2007)
Radu M. $ecareanu, David Albonesi, Eby G. Friedman
Abstract-- A circuit to dynamically raconfigure the clock frequency of a synchronous digital system according to the changing needs of the application is described in this paper. The circuit changes...
Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Peter Cook, David Albonesi
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a...
Rajeev Balasubramonian, Sandhya Dwarkadas, David Albonesi
Dynamic superscalar processors execute instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a direct impact...
Electrical and optical on-chip interconnects in scaled microprocessors (2005)
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David Albonesi, Eby G. Friedman
Abstract — Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to...
A Circuit Level Implementation of an Adaptive Issue Queue for Power-Aware Microprocessors (2001)
Alper Buyuktosunoglu, David Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter Cook
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a...
Dynamic Memory Hierarchy Performance Optimization (2000)
Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas, Hya Dwarkadas
Although microprocessor performance continues to increase at a rapid pace, the growing processor-memory speed gap threatens to limit future performance gains. In this paper, we propose a novel...
An adaptive issue queue for reduced power at high performance (2000)
Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter Cook, David Albonesi
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a...
Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, Hya Dwarkadas
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that leverages repeater...
An adaptive issue queue for reduced power at high performance (2000)
Alper Buyuktosunoglu, Alper Buyuktosunoglu, Stanley Schuster, Stanley Schuster, David Brooks, David Brooks, ...
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Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu, Hya Dwarkadas
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that leverages repeater...