On-chip Optical Interconnect Roadmap: Challenges and Critical Directions (2008)
Mikhail Haurylau, Hui Chen, Jidong Zhang, Guoqing Chen, Nicholas A. Nelson, David H. Albonesi, ...
Abstract — Intrachip optical interconnects can outperform electrical wires but the required parameters for optical components are yet unknown. Here the ITRS is used as a reference point to derive...
The Energy Impact of Aggressive Loop Fusion ∗ (2008)
Yongkang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi
Loop fusion combines corresponding iterations of different loops. It is traditionally used to decrease program run time, by reducing loop overhead and increasing data locality. In this paper,...
Wael El-essawy, David H. Albonesi
Simultaneous Multi-Threading, although effective in increasing processor throughput, exacerbates the inductive noise problem such that more expensive electronic solutions are required even with the...
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches ⋆ (2008)
Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phases within the same...
ABSTRACT Tradeoffs in Power-Efficient Issue Queue Design (2008)
Alper Buyuktosunoglu, David H. Albonesi
A major consumer of microprocessor power is the issue queue. Several microprocessors, including the Alpha 21264 and POWER4 ¢¡ use a compacting latch-based issue queue design which has the...
The Energy Impact of Aggressive Loop Fusion (2008)
Yongkang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi
scott,cding¥ Loop fusion combines corresponding iterations of different loops. It is traditionally used to decrease program run time, by reducing loop overhead and increasing data locality. In this...
Wael El-essawy, David H. Albonesi
Clock gating is an effective means for reducing average power consumption. However, clock gating can exacerbate maximum cycleto-cycle current swings, or the step-power (Ldi/dt) problem. We present a...
Managing Static Leakage Energy in Microprocessor Functional Units £ (2008)
Steven Dropshoý, Volkan Kursun, David H. Albonesi, Hya Dwarkadasý, Eby G. Friedman
Static energy due to subthreshold leakage current is projected to become a major component of the total energy in high performance microprocessors. Many studies so far have examined and proposed...
The Energy Impact of Aggressive Loop Fusion ∗ (2008)
Yongkang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi
Loop fusion combines corresponding iterations of different loops. It is traditionally used to decrease program run time, by reducing loop overhead and increasing data locality. In this paper,...
M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi
The microprocessor industry is rapidly moving to the use of multicore chips as general-purpose processors. Whereas the current generation of chip multiprocessors (CMPs)—such as the IBM Power5, 1...
Energy dissipation has become a critical design con-straint... (2008)
Steven Dropshoy, Volkan Kursun, David H. Albonesi, Hya Dwarkadas, Eby G. Friedman
Abstract Static energy due to subthreshold leakage current is pro-jected to become a major component of the total energy in high performance microprocessors. Many studies so farhave examined and...
On-Chip Optical Interconnect for Reduced Delay Uncertainty (2008)
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas A. Nelson, David H. Albonesi, Eby G. Friedman
Abstract — Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to...
David H. Albonesi, Israel Koren
: We present a methodology for comprehensively evaluating architectural and technological alternatives of the processor, cache hierarchy, system interconnect, and main memory subsystems. We use the...
A Methodology for the In-Depth Analysis of Cache Hierarchy Design Alternatives (2007)
David H. Albonesi, Israel Koren
: As the speed gap between microprocessors and board-level technology continues to widen, developing a performance-optimal cache hierarchy remains a critical element in the design of high-performance...
Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, ...
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by...
Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a...
Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Modern superscalar processors use wide instruction issue widths and out-of-order execution in order to increase instruction-level parallelism (ILP). Because instructions must be committed in order so...
Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems (2007)
David H. Albonesi, Israel Koren
Next generation, wide-issue processors will require greater memory bandwidth than provided by present memory hierarchy designs. We propose techniques for increasing the memory bandwidth of...
Microarchitectural Trade-offs in the Design of a Scalable Clustered Microprocessor (2007)
Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained...
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches (2007)
Lopez, Sonia, Dropsho, Steven, Albonesi, David H., Garnica, Oscar, Lanchares, Juan
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phases within the same...
Sato, Mitsuhisa, Vasell, Jesper, Albonesi, David H., Roh, Lucas, Sur, S., Yasugi, M., ...
Contents: Part I-High Performance Architectures; Part II-Code Generation for Multithreaded and Dataflow Architectures; Part III-Memory and Cache Issues; Part IV-Distributed Memory Machines; Part...
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas A. Nelson, David H. Albonesi, Eby G. Friedman
Abstract — As CMOS technology is scaled, it has become increasingly difficult for conventional copper interconnect to satisfy different design requirements. On-chip optical interconnect has been...
Leveraging optical technology in future bus-based chip multiprocessors (2006)
Nevin Kırman, Meyrem Kırman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, ...
Although silicon optical technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the development of on-chip...
Cache Design Options for a Clustered Multithreaded Architecture (2005)
Garg, Rajeev, El-Moursy, Ali, Dwarkadas, Sandhya, Albonesi, David H., Rivers, Jude A., Srinivasan, Viji
The design of the memory hierarchy in a multi-core architecture is a critical component since it must meet the capacity (in terms of bandwidth and low latency) and coordination requirements of...
Optical interconnect roadmap: challenges and critical directions (2005)
Mikhail Haurylau, Associate Member, Guoqing Chen, Hui Chen, Jidong Zhang, Nicholas A. Nelson, ...
Abstract—Intrachip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately solve the communication bottleneck in high-performance integrated circuits....
Nicholas Nelson, Gregory Briggs, Mikhail Haurylau, Guoqing Chen, Hui Chen, David H. Albonesi, ...
The relentless pursuit of Moore’s Law by the semiconductor industry has yielded significant increases in performance, but at the cost of greater power dissipation. As CMOS technology continues to...
Optical interconnect roadmap: challenges and critical directions (2005)
Mikhail Haurylau, Hui Chen, Jidong Zhang, Guoqing Chen, Nicholas A. Nelson, David H. Albonesi, ...
Abstract — Intrachip optical interconnects can outperform electrical wires but the required parameters for optical components are yet unknown. Here the ITRS is used as a reference point to derive...
Semeraro, Greg, Albonesi, David H., Dropsho, Steven, Magklis, Grigorios, Scott, Michael L.
Microprocessors are traditionally designed to provide “best overall” performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques...
Hiding Synchronization Delays in a GALS Processor Microarchitecture (2004)
Semeraro, Greg, Albonesi, David H., Magklis, Grigorios, Scott, Michael L., Dropsho, Steven, Dwarkadas, Sandhya
We analyze an Alpha 21264-like Globally–Asynchronous, Locally–Synchronous (GALS) processor organized as a Multiple Clock Domain (MCD) microarchitecture and identify the architectural features of...
Dynamically Matching ILP Characteristics Via a Heterogeneous Clustered Microarchitecture (2004)
Chen, Lei, Albonesi, David H., Dropsho, Steven
Applications vary in the degree of instruction level parallelism (ILP) available to be exploited by a superscalar processor. The ILP can also vary significantly within an application. On one end of...
Dynamically Trading Frequency for Complexity in a GALS Microprocessor (2004)
Dropsho, Steven, Semeraro, Greg, Albonesi, David H., Magklis, Grigorios, Scott, Michael L.
Microprocessors are traditionally designed to provide “best overall” performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques...
Dynamically trading frequency for complexity in a gals microprocessor (2004)
Steven Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott
Microprocessors are traditionally designed to provide “best overall ” performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques...
Greg Semeraro, David H. Albonesi, Steven Dropsho, Grigorios Magklis, Michael L. Scott
Microprocessors are traditionally designed to provide “best overall ” performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques...
Dynamically Trading Frequency for Complexity in a GALS Microprocessor (2004)
Steven Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott
Microprocessors are traditionally designed to provide "best overall" performance across a wide range of applications and operating environments. Several groups have proposed hardware...
SCHOOL ADDRESS: PERMANENT ADDRESS: (2004)
Jonathan Aaron Winter, Advisor Professor, David H. Albonesi, Professor David Albonesi
Developed operating system scheduling algorithms for assigning threads to heterogeneous processor cores. Studied SMT thread management techniques to improve microprocessor lifetime reliability....
Hiding Synchronization Delays in a GALS Processor Microarchitecture (2004)
Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Hya Dwarkadas
We analyze an Alpha 21264-like Globally–Asynchronous, Locally–Synchronous (GALS) processor organized as a Multiple Clock Domain (MCD) microarchitecture and identify the architectural features of...
The Energy Impact of Aggressive Loop Fusion (2003)
Zhu, YongKang, Magklis, Grigorios, Scott, Michael L., Ding, Chen, Albonesi, David H.
Loop fusion combines corresponding iterations of different loops. As shown in previous work, it can often decrease program run time by reducing the overhead of loop control and effective address...
Dynamic Data Dependence Tracking and Its Application to Branch Prediction (2003)
Chen, Lei, Dropsho, Steven, Albonesi, David H.
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundamental limit to...
Magklis, Grigorios, Scott, Michael L., Semeraro, Greg, Albonesi, David H., Dropsho, Steven
A Multiple Clock Domain (MCD) processor addresses the challenges of clock distribution and power dissipation by dividing a chip into several (coarse-grained) clock domains, allowing frequency and...
Semeraro, Greg, Albonesi, David H., Dropsho, Steven, Magklis, Grigorios, Scott, Michael L.
Microprocessors are traditionally designed to provide “best overall” performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques...
Dynamically Tuning Processor Resources with Adaptive Processing (2003)
Albonesi, David H., Balasubramonian, Rajeev, Dropsho, Steven, Dwarkadas, Sandhya, Friedman, Eby G., Huang, Michael C., ...
The productivity of modern society has become inextricably linked to its ability to produce energy-efficient computing technology. Increasingly sophisticated mobile computing systems, powered for...
Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor (2003)
Magklis, Grigorios, Semeraro, Greg, Albonesi, David H., Dropsho, Steven, Dwarkadas, Sandhya, Scott, Michael L.
Multiple clock domains is one solution to the increasing problem of propagating the clock signal across increasingly larger and faster chips. The ability to independently scale frequency and voltage...
Front-end policies for improved issue efficiency in SMT processors (2003)
Ali El-moursy, David H. Albonesi
The performance and power optimization of dynamic superscalar microprocessors requires striking a careful balance between exploiting parallelism and hardware simplification. Hardware structures which...
Dynamic Data Dependence Tracking and its Application to Branch Prediction (2003)
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundamental limit to...
Energy efficient co-adaptive instruction fetch and issue (2003)
Alper Buyuktosunoglu, Tejas Karkhanis Y, David H. Albonesi, Pradip Bose Z
Front-end instruction delivery accounts for a significant fraction of the energy consumed in a dynamic superscalar processor. The issue queue in these processors serves two crucial roles: it bridges...
Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steven Dropsho
A Multiple Clock Domain (MCD) processor addresses the challenges of clock distribution and power dissipation by dividing a chip into several (coarse-grained) clock domains, allowing frequency and...
Energy efficient co-adaptive instruction fetch and issue (2003)
Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose
Front-end instruction delivery accounts for a significant fraction of the energy consumed in a dynamic superscalar processor. The issue queue in these processors serves two crucial roles: it bridges...
The Energy Impact of Aggressive Loop Fusion (2003)
Yongkang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi
Loop fusion combines corresponding iterations of different loops. As shown in previous work, it can often decrease program run time by reducing the overhead of loop control and effective address...
Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steven Dropsho
A Multiple Clock Domain (MCD) processor addresses the challenges of clock distribution and power dissipation by dividing a chip into several (coarse-grained) clock domains, allowing frequency and...
Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steven Dropsho
A Multiple Clock Domain (MCD) processor addresses the challenges of clock distribution and power dissipation by dividing a chip into several (coarse-grained) clock domains, allowing frequency and...
Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor (2003)
Grigorios Magklis, Greg Semeraro, David H. Albonesi, Steven G. Dropsho, Sandhya Dwarkadas, ...
This article briefly summarizes both of these approaches and compares their performance against a near-optimal offline technique
A dynamically tunable memory hierarchy (2003)
Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Hya Dwarkadas
The widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and translation lookaside buffer (TLB) hierarchy...
Dynamically managing the communication-parallelism trade-off in future clustered processors (2003)
Rajeev Balasubramonian, Hya Dwarkadas, David H. Albonesi
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained...
Energy efficient co-adaptive instruction fetch and issue (2003)
Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose
Front-end instruction delivery accounts for a significant fraction of the energy consumed in a dynamic superscalar processor. The issue queue in these processors serves two crucial roles: it bridges...
Dynamically managing the communication-parallelism trade-off in future clustered processors (2003)
Rajeev Balasubramonian, Hya Dwarkadas, David H. Albonesi
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained...
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power (2002)
Dropsho, Steven, Buyuktosunoglu, Alper, Balasubramonian, Rajeev, Albonesi, David H., Dwarkadas, Sandhya, Semeraro, Greg, ...
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by...
Microarchitectural Trade-Offs in the Design of a Scalable Clustered Microprocessor (2002)
Balasubramonian, Rajeev, Dwarkadas, Sandhya, Albonesi, David H.
Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained...
Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture (2002)
Semeraro, Greg, Albonesi, David H., Dropsho, Steven, Magklis, Grigorios, Dwarkadas, Sandhya, Scott, Michael L.
We describe the design, analysis, and performance of an on-line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MCD microarchitecture...
Managing Static Leakage Energy in Microprocessor Functional Units (2002)
Dropsho, Steven, Kursun, Volkan, Albonesi, David H., Dwarkadas, Sandhya, Friedman, Eby G.
Static energy due to subthreshold leakage current is projected to become a major component of the total energy in high performance microprocessors. Many studies so far have examined and proposed...
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power (2002)
Dropsho, Steven, Buyuktosunoglu, Alper, Balasubramonian, Rajeev, Albonesi, David H., Dwarkadas, Sandhya, Semeraro, Greg, ...
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by...
Tradeoffs in power-efficient issue queue design (2002)
Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley E. Schuster
A major consumer of microprocessor power is the issue queue. Several microprocessors, including the Alpha 21264 and POWER4 TM use a compacting latch-based issue queue design which has the advantage...
Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Hya Dwarkadas, Michael L. Scott
As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe...
A microarchitectural-level step-power analysis tool (2002)
Wael El-essawy, David H. Albonesi, Balaram Sinharoy
Clock gating is an effective means for reducing average power consumption. However, clock gating can exacerbate maximum cycleto-cycle current swings, or the step-power (Ldi/dt) problem. We present a...
An Oldest-First Selection Logic Implementation for NonCompacting Issue Queues (2002)
Alper Buyuktosunoglu, Ali El-moursy, David H. Albonesi
Abstract--- Microprocessor power dissipation is a growing concern, so much so that it threatens to limit future performance improvements. A major consumer of microprocessor power is the issue queue....
Dynamic frequency and voltage control for a multiple clock domain microarchitecture (2002)
Greg Semeraro, David H. Albonesi, Steven G. Dropsho, Grigorios Magklis, Hya Dwarkadas, Michael L. Scott
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MCD microarchitecture...
Managing static leakage energy in microprocessor functional units (2002)
Steven Dropsho, Volkan Kursun, David H. Albonesi, Hya Dwarkadas, Eby G. Friedman
Static energy due to subthreshold leakage current is projected to become a major component of the total energy in high performance microprocessors. Many studies so far have examined and proposed...
Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Hya Dwarkadas, Michael L. Scott
As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe...
Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Hya Dwarkadas, Michael L. Scott
As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing chal-lenge to the designers of singly-clocked, globally syn-chronous systems. We describe...
Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Hya Dwarkadas, Michael L. Scott
As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe...
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power (2002)
Steve Dropsho Alper, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Hya Dwarkadas, Greg Semeraro, ...
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by...
Integrating adaptive on-chip storage structures for reduced dynamic power (2002)
Steve Dropsho, Alper Buyuktosunogluz, Rajeev Balasubramoniany, David H. Albonesi, Hya Dwarkadasy, Greg Semeraroz, ...
The philosophy of high performance microprocessordesign has been to push for ever greater performance as
Integrating adaptive on-chip storage structures for reduced dynamic power (2002)
Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Hya Dwarkadas, Greg Semeraro, ...
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by...
Dynamically Allocating Processor Resources between Nearby and Distant ILP (2001)
Balasubramonian, Rajeev, Dwarkadas, Sandhya, Albonesi, David H.
Modern superscalar processors use wide instruction issue widths and out-of-order execution in order to increase instruction-level parallelism (ILP). Since instructions must be committed in order so...
A High Performance Two-Level Register File Organization (2001)
Balasubramonian, Rajeev, Dwarkadas, Sandhya, Albonesi, David H.
Dynamic superscalar processors execute instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a direct impact...
Reducing the Complexity of the Register File in Dynamic Superscalar Processors (2001)
Rajeev Balasubramonian Sandhya, Sandhya Dwarkadas, David H. Albonesi
Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a...
Dynamically allocating processor resources between nearby and distant ILP (2001)
Rajeev Balasubramonian, Hya Dwarkadas, David H. Albonesi
Modern superscalar processors use wide instruction issue widths and out-of-order execution in order to increase instruction-level parallelism (ILP). Because instructions must be committed in order so...
Reducing the complexity of the register file in dynamic superscalar processors (2001)
Rajeev Balasubramonian, Hya Dwarkadas, David H. Albonesi
Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a...
Selective Cache Ways: On-Demand Cache Resource Allocation (2000)
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application requirements....
Runtime Reconfiguration Techniques for Efficient General Purpose Computation (2000)
Bingxiong Xu And, Bingxiong Xu, David H. Albonesi
: Because of their widespread use, general purpose microprocessors are called upon to execute an increasingly diverse set of applications. Due to their static organization, these devices often...
STATS: A framework for microprocessor and system-level design space exploration (1999)
David H. Albonesi, Israel Koren
processors As microprocessor-based systems grow in complexity, and the processor-memory speed gap widens further, more emphasis needs to be placed on early design space exploration in order to...
Bingxiong Xu And, Bingxiong Xu, David H. Albonesi
Although many studies have been performed to determine the overall parallelism of various applications, little is known about how parallelism changes dynamically during program execution. In this...
We present a combined architectural and circuit technique for reducing the energy dissipation of microprocessor memory structures. This approach exploits the subarray partitioning of high speed...
Selective Cache Ways: On-Demand Cache Resource Allocation (1999)
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that save energy by better matching of on-chip resources to application requirements....
Allocation David Albonesi, David H. Albonesi
Increasing levels of microprocessor power dissipation call for new approaches at the architectural level that saveenergyby better matching of on-chip resources to application requirements. Selective...
A Performance On-Demand Approach to Power-Efficient Computing (1998)
Albonesi, David H., Dwarkadas, Sandhya, Friedman, Eby G., Scott, Michael L.
Complexity-Adaptive Processing (CAP) addresses increasing microprocessor power dissipation through on-the-fly, low-cost hardware adaptation and related circuit techniques so as to better match...
Dynamic IPC/Clock Rate Optimization (1998)
David Albonesi Dept, David H. Albonesi
Current microprocessor designs set the functionality and clock rate of the chip at design time based on the configuration that achieves the best overall performance over a range of target...
The Inherent Energy Efficiency of Complexity-Adaptive Processors (1998)
Conventional microprocessor designs that statically set the functionality of the chip at design time may waste considerable energy when running applications whose requirements are poorly matched to...
David H. Albonesi, Israel Koren
The design of high performance computing systems requires many design decisions based on performance, cost, power consumption, and possibly other criteria. Decisions made in the early, high-level...
David H. Albonesi, Israel Koren
: Several approximate Mean Value Analysis (MVA) shared memory multiprocessor models have been developed and used to evaluate a number of system architectures. In recent years, the use of superscalar...
An Analytical Model of High Performance Superscalar-Based Multiprocessors (1995)
David H. Albonesi, Israel Koren
Several shared memory multiprocessor models using approximate Mean Value Analysis (MVA) have been developed and used to evaluate a number of system architectures. Since this time, the complexity of...
Tradeoffs in the Design of Single Chip Multiprocessors (1994)
David H. Albonesi, Israel Koren
: By the end of the decade, as VLSI integration levels continue to increase, building a multiprocessor system on a single chip will become feasible. In this paper, we propose to analyze the tradeoffs...