Fully Compatible Integration of High Density Embedded DRAM with 65nm CMOS Technology (CMOS5) (2009)
Y. Matsubara, M. Habu, S. Matsuda, K. Honda, E. Morifuji, T. Yoshida, ...
65nm node SoC technology has been achieved to show good yield of 8M bit DRAM ADM using tapered BF2 implantation without additional mask step, which cell size is 0.11um 2 [1], with 3 layers hybrid...
An Insulator-Lined Silicon Substrate-Via Technology With (2008)
H. S. Momose, E. Morifuji, T. Yoshitomi, T. Ohguro, M. Saito, T. Morimoto, ...
[4] S. F. Tin, A. A. Osman, K. Mayaram, and C. Hu, “A simple subcuircuit extension of the BSIM3v3 model for RF CMOS design, ” Solid-State
A single-chip CMOS transceiver front-end for DCS-1800 wireless communications (2000)
Itoh, N, Craninckx, J, ...
This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 mu m CMOS technology. The presented prototype integrates the LNA,...