Eby G. Friedman

On-Chip Power Distribution Grids with Multiple Supply Voltages for High Performance Integrated Circuits ABSTRACT (2008)

A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active power consumption...

Design, Performance (2008)

Multiple supply voltages are often utilized to decrease power dissipation in high performance integrated circuits. On-chip power distribution grids with multiple supply voltages are discussed in this...

Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Eby G. Friedman, David Albonesi

Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the...

Dynamically Tuning Processor Resources (2008)

Steven G, Eby G. Friedman, Michael C, Volkan Kursun, Michael L. Scott, Greg Semeraro, ...

with Adaptive

A Universal CMOS Voltage Interface Circuit (2008)

Radu M. Secareanu, Eby G. Friedman, Juan Becerra, Scott Warner

Abstract | A CMOS interface circuit to transfer a digital signal between two circuits of di erent supply voltages is described. The interface can be used, for example, between3volt and 5 volt or...

A BULK-DRIVEN CMOS OTA WITH 68 dB DC GAIN (2008)

Jonathan Rosenfeld, Mücahit Kozak, Eby G. Friedman

An ultra-low voltage rail-to-rail operational transconductance amplifier (OTA) based on a standard digital 0.18 �m CMOS process is described in this paper. Techniques for designing a 0.8 volt fully...

Transactions Briefs__________________________________________________________________ Shielding Effect of On-Chip Interconnect Inductance (2008)

Transparent Repeaters 1 (2008)

Abstract—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective...

Radu M. Secareanu, Eby G. Friedman

Abstract--The concept of a "transparent repeater a ~" which is an amplifier circuit designed to minimize the delay introduced by highly resistive interconnect lines in high speed...

Managing Static Leakage Energy in Microprocessor Functional Units £ (2008)

Steven Dropshoý, Volkan Kursun, David H. Albonesi, Hya Dwarkadasý, Eby G. Friedman

Static energy due to subthreshold leakage current is projected to become a major component of the total energy in high performance microprocessors. Many studies so far have examined and proposed...

On-die Decoupling Capacitance: Frequency Domain Analysis ofActivity Radius (2008)

Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman

Abstract-On-die capacitances interact with the inductance capacitance is provided by specially designed circuits and resistance of the power distribution network to supply whose primary role is...

Timing of Large RSFQ Digital Circuits (2008)

Kris Gaj, Eby G. Friedman, Marc J. †feldman

Abstractã This paper analyzes RSFQ timing from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and...

Quasi-Resonant Interconnects: (2008)

A Low, Power Design Methodology, Jonathan Rosenfeld, Eby G. Friedman

Abstract — Design and analysis guidelines for resonant interconnect networks are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of the on-chip...

CHOICE OF THE OPTIMUM TIMING SCHEME FOR RSFQ DIGITAL CIRCUITS › (2008)

Kris Gaj, Eby G. Friedman, Marc J. Feldman

Rapid Single Flux Quantum (RSFQ) logic is a superconducting digital circuit technology that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high...

Speed and Noise Immunity Enhanced Low Power Dynamic Circuits (2008)

Two-phase Clocking for Medium to Large RSFQ Circuits (2008)

Abstract – Four different dynamic circuit techniques are proposed in this paper for lowering the active mode power consumption, increasing the speed, enhancing the noise immunity, and reducing the...

Kris Gaj, Eby G. Friedman, Marc J. †feldman

Abstractã In this article a novel two-phase clocking scheme applicable to RSFQ circuits of any complexity is introduced. We show that high performance, robustness, and design simplicity may justify...

Dynamically Tuning Processor Resources (2008)

Steven G, Eby G. Friedman, Michael C, Volkan Kursun, Michael L. Scott, Greg Semeraro, ...

with Adaptive

INTEGRATION, the VLSI journal 38 (2004) 205–225 Optimum wire sizing of RLC interconnect with repeaters (2008)

Design, Performance (2008)

Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive and can affect signal behavior. The line inductance should therefore be considered in...

Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Eby G. Friedman, David Albonesi

Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the...

Substrate and Ground Noise Interactions in Mixed-Signal Circuits (2008)

Emre Salman, Eby G. Friedman

Abstract — The interaction of the substrate with the inductive on-chip ground distribution network is analyzed in this paper. A transistor level approach is presented to illustrate the effects of...

ESSCIRC 2002 Domino Logic with Dynamic Body Biased Keeper (2008)

Algorithms implemented in hardware, VLSI (2008)

A dynamic body biased keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is...

Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic (2008)

A complex ±1 multiplier is an integral element in modern CDMA communication systems, specifically as a pseudonoise code scrambler/descrambler. Therefore, an efficient implementation is essential to...

Substrate Coupling in Digital Circuits in Mixed-Signal Smart-Power Systems (2008)

Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, ...

Abstract—This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work...

Transactions Briefs A Hybrid Radix-4/Radix-8 Low Power Signed Multiplier Architecture (2008)

Brian S. Cherkauer, Eby G. Friedman

Abstract—A hybrid radix-4/radix-8 architecture targeted for high bit, general purpose, digital multipliers is presented as a compromise between the high speed of a radix-4 multiplier architecture...

Energy dissipation has become a critical design con-straint... (2008)

Steven Dropshoy, Volkan Kursun, David H. Albonesi, Hya Dwarkadas, Eby G. Friedman

Abstract Static energy due to subthreshold leakage current is pro-jected to become a major component of the total energy in high performance microprocessors. Many studies so farhave examined and...

On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits (2008)

General Terms: Design (2008)

Abstract- Switching digital circuits produce current peaks which result in voltage fluctuations on the power supply lines due to the inductive behavior of on-chip and chip-to-package interconnects. A...

Transactions Briefs__________________________________________________________________ Exponentially Tapered H-Tree Clock Distribution Networks (2008)

Orthogonal variable spreading factor (OVSF) codes are standard in third generation UMTS cellular systems. The efficient generation of these codes is essential for reducing the area and power of...

A 0.8 Volt High Performance OTA Using Bulk-Driven MOSFETs (2008)

Abstract—Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces...

Jonathan Rosenfeld, Mucahit Kozak, Eby G. Friedman

An ultra-low voltage rail-to-rail folded-cascode operational transconductance amplifier (OTA) based on a standard digital 0.18 µm CMOS process is described in this paper. A bulkdriven MOSFET...

On-Chip Optical Interconnect for Reduced Delay Uncertainty (2008)

Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas A. Nelson, David H. Albonesi, Eby G. Friedman

Abstract — Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to...

A HIGH PRECISION CMOS CURRENT MIRROR / DIVIDER (2008)

Radu M. Secareanu, Eby G. Friedman

Abstract – A current mirror topology is proposed that provides very high precision, design insensitive up and down mirrored current, operation over a wide power supply range, straightforward...

LOW POWER FLEXIBLE RAKE RECEIVERS FOR WCDMA (2008)

A Low Power Thyristor-Based CMOS Programmable Delay Element (2008)

Abstract: Two low power flexible Rake receiver architectures are presented. The first architecture exploits the statistical distribution of multipath delays in wireless channels to reduce power...

Junmou Zhang, Simon R. Cooper, Andrew R. Lapietra, Michael W. Mattern, Robert M. Guidash, Eby G. Friedman

Abstract — A delay element insensitive to power supply and temperature variations become important as circuit speeds increase. A delay element, based on a CMOS thyristor, is proposed in this paper....

Analysis of Buck Converters for On-Chip Integration With a Dual Supply Voltage Microprocessor (2008)

S. Lin, Y. Lin, T. Hwang, N. C. Chou, L. T. Liu, C. K. Cheng, ...

Sweely, “Building and using a highly parallel programmable logic

Efficient Placement of Distributed On-Chip Decoupling Capacitors in Nanoscale ICs (2008)

On-Chip Power Distribution Grids with Multiple Supply Voltages for High Performance Integrated Circuits ABSTRACT (2008)

Abstract — Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on the die based on an...

Inductance Effects in RLC Trees (2007)

Multiple supply voltages are often utilized to decrease power dissipation in high performance integrated circuits. On-chip power distribution grids with multiple supply voltages are discussed in this...

Inductance Effects in RLC Trees (2007)

Abstract-- A closed form solution for characterizing voltage-based signals in an RLC tree is presented. The closed form solution is used to derive figures of merit to characterize the effects of...

Yehea Ismail, Eby G. Friedman, Jose L. Neves

A closed form solution for characterizing voltage-based signals in an RLC tree is presented. This closed form solution is used to derive figures of merit to characterize the effects of inductance at...

Timing of Large RSFQ Digital Circuits (2007)

Kris Gaj, Eby G. Friedman, Marc J. +feldman

ã This paper analyzes RSFQ timing from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous,...

DEMONSTRATION OF SPEED ENHANCEMENTS ON AN INDUSTRIAL CIRCUIT THROUGH APPLICATION OF NON-ZERO CLOCK SKEW SCHEDULING (2007)

Dirnitrios Velenis, Kevin T. Tang, Victor Adler, Franklin Baez, Eby G. Friedman

A demonstration of the application of non-zero clock skew scheduling to enhance the speed characteristics of several functional unit blocks in a high performance processor is presented. It is shown...

A DYNAMIC RECONFIGURABLE CLOCK GENERATOR (2007)

Radu M. $ecareanu, David Albonesi, Eby G. Friedman

Abstract-- A circuit to dynamically raconfigure the clock frequency of a synchronous digital system according to the changing needs of the application is described in this paper. The circuit changes...

Estimation of Transient Voltage Fluctuations in the CMOS-Based Power Distribution Networks (2007)

An Substrate Noise Circuit for Accurately Testing Mixed-Signal ICs (2007)

Abstract--Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and...

Weize Xu, Eby G. Friedman

Abstract- A substrate coupling noise measurement technique is presented in this paper. The proposed on-chip test circuit can accurately and efficiently measure substrate coupling noise in any type of...

Retiming and Clock Scheduling for Digital Circuit Optimization (2007)

Xun Liu, Student Member, Marios C. Papaefthymiou, Eby G. Friedman

Abstract—This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimization problems are...

Uniform Repeater Insertion in Trees (2007)

Victor Adler, Eby G. Friedman

Abstract—Repeater insertion can be used to overcome the quadratic increase in the time required for a signal to propagate through an interconnect. A new timing model, based on short-channel...

Toward a Systematic Design Methodology for Large Multigigahertz Rapid Single Flux Quantum Circuits (2007)

Kris Gaj, Quentin P. Herr, Victor Adler, Darren K. Brock, Eby G. Friedman, Marc J. Feldman

Abstract — Rapid single flux quantum (RSFQ) digital circuits have reached the level of medium- to large-scale of integration. At this level, existing design methodologies, developed specifically...

CMOS VOLTAGE INTERFACE CIRCUIT FOR (2007)

Low Power Systems, Volkan Kursun, Radu M. Secareanu, Eby G. Friedman

A bi-dimctional CMOS voltage interface circuit is proposed for applications that require signal transfer between two circuits operating at different voltage levels. The cir-cuit can also be used as a...

Transient Analysis of a CMOS Inverter Driving Resistive Interconnect (2007)

CHOICE OF THE OPTIMUM TIMING SCHEME FOR RSFQ DIGITAL CIRCUITS (2007)

Abstract — Expressions characterizing the output voltage and propagation delay of a CMOS inverter driving a resistive-capacitive interconnect are presented in this paper. The MOS transistors are...

Kris Gaj, Eby G. Friedman, Marc J. Feldman

Rapid Single Flux Quantum (RSFQ) logic is a superconducting digital circuit technology that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high...

Two-phase Clocking for Medium to Large RSFQ Circuits (2007)

Kris Gaj, Eby G. Friedman, Marc J. +feldman

Abstract In this article a novel two-phase clocking scheme applicable to RSFQ circuits of any complexity is introduced. We show that high performance, robustness, and design simplicity may justify...

Transient Analysis of a CMOS Inverter Driving Resistive Interconnect (2007)

Physical Design to Improve the Noise Immunity of Digital Circuits in a Mixed-Signal Smart-Pow er System (2007)

Abstract — Expressions characterizing the output voltage and propagation delay of a CMOS inverter driving a resistive-capacitive interconnect are presented in this paper. The MOS transistors are...

Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Thomas E. Watrobski, Christopher Morton, ...

A bstract | Theoretical, sim ulation, and experimental analysis and data are presented, discussing physical design techniques which in uence the noise behavior of digital circuits in a mixed-signal...

Unified Logical Effort- A Method for Delay Evaluation and Minimization in Logic Paths with RC Interconnect (2007)

Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny

Abstract- A model for delay evaluation and minimization in paths composed of logic gates and RC wires is presented. The method, Unified Logical Effort (ULE), provides closed-form conditions for...

Substrate Noise Reduction Based on Noise Aware Cell Design (2007)

Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin

Abstract — A substrate biasing methodology is introduced based on modifying standard cells by inserting dedicated substrate contacts in those cells behaving as aggressive digital noise generators....

Maximum Effective Distance of On-Chip Decoupling Capacitors in Power Distribution Grids (2006)

Abstract INTEGRATION, the VLSI journal 40 (2007) 461–472 Wire shaping of RLC interconnects $ (2006)

Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the available white space on a die. The efficacy of on-chip...

SIZING CMOS INVERTERS WITH MILLER EFFECT AND THRESHOLD VOLTAGE VARIATIONS (2006)

The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tapering more...

Boris Andreev, Edward L. Titlebaum, Eby G. Friedman

The maximum speed of synchronous circuits is generally constrained by the worst case propagation delay, which limits the system clock frequency. Various techniques exist to manage the circuit delay,...

On-chip copper-based vs. optical interconnects: delay uncertainty, latency, power, and bandwidth density comparative predictions (2006)

Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas A. Nelson, David H. Albonesi, Eby G. Friedman

Abstract — As CMOS technology is scaled, it has become increasingly difficult for conventional copper interconnect to satisfy different design requirements. On-chip optical interconnect has been...

Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times (2006)

Emre Salman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar, Eby G. Friedman

Abstract — A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static timing...

3-D Topologies for Networks-on-Chip (2006)

Vasilis F. Pavlidis, Student Member, Eby G. Friedman

Abstract—Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3-D NoC are compared to that of 2-D NoC. Physical...

Optimum wire tapering for minimum power dissipation of RLC interconnects (2006)

On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits (2006)

Abstract-The optimum tapered structure for RLC inter-RLC interconnect connect to minimize transient power dissipation is determined. Wire tapering can reduce the power dissipated by a circuit by-up...

Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny

Abstract—On-chip power distribution grids with multiple supply voltages are discussed in this paper. Two types of interdigitated and paired power distribution grids with multiple supply voltages...

Design Methodology for Global Resonant H-Tree Clock Distribution Networks (2006)

Jonathan Rosenfeld, Eby G. Friedman

Abstract- Design guidelines for resonant H-tree clock A comprehensive, constraint free, and robust design methdistribution networks are presented in this paper. A dis- odology for resonant H-tree...

Optical interconnect roadmap: challenges and critical directions (2005)

Mikhail Haurylau, Associate Member, Guoqing Chen, Hui Chen, Jidong Zhang, Nicholas A. Nelson, ...

Abstract—Intrachip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately solve the communication bottleneck in high-performance integrated circuits....

Alleviating Thermal Constraints while Maintaining Performance Via Silicon-Based On-Chip Optical Interconnects (2005)

Nicholas Nelson, Gregory Briggs, Mikhail Haurylau, Guoqing Chen, Hui Chen, David H. Albonesi, ...

The relentless pursuit of Moore’s Law by the semiconductor industry has yielded significant increases in performance, but at the cost of greater power dissipation. As CMOS technology continues to...

Interconnect delay minimization through interlayer via placement (2005)

Vasilis F. Pavlidis, Eby G. Friedman

[pavlidis, friedman] @ ece.rochester.edu The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable...

Cascode buffer for monolithic voltage conversion operating at high input supply voltages (2005)

Volkan Kursun, Gerhard Schrom, Vivek K. De, Eby G. Friedman, Siva G. Narendra

A high-to-low switching DC-DC converter that operates at input supply voltages up to two times as high as the maximum voltage permitted in a nanometer CMOS technology is proposed in this paper. The...

Optical interconnect roadmap: challenges and critical directions (2005)

Mikhail Haurylau, Hui Chen, Jidong Zhang, Guoqing Chen, Nicholas A. Nelson, David H. Albonesi, ...

Abstract — Intrachip optical interconnects can outperform electrical wires but the required parameters for optical components are yet unknown. Here the ITRS is used as a reference point to derive...

Electrical and optical on-chip interconnects in scaled microprocessors (2005)

Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David Albonesi, Eby G. Friedman

Abstract — Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to...

Scaling Trends of On-Chip Power Distribution Noise (2004)

Andrey V. Mezhiba, Eby G. Friedman

The design of power distribution networks in high performance integrated circuits has become significantly more challenging with recent advances in process technology. As on-chip currents exceed tens...

@ 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands. Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages (2004)

Volkan Kursun, Siva G. Narendra, Vivek K. Del, Eby G. Friedman

Abstract. A caseode bridge circuit for monolithic switching DC-DC converters operating at high input voltages is proposed in this paper. The proposed circuit can also be used as an I/O buffer to...

A high-speed CMOS op-amp design technique using negative miller capacitance (2004)

Boaz Shem-tov, Mücahit Kozak, Eby G. Friedman

A method is presented in this paper for the design of high speed CMOS Operational Amplifiers (Op-Amp). The Op-Amp consists of an Operational Transconductance Amplifier (OTA) followed by an output...

Low-voltage-swing Monolithic DC-DC Conversion (2004)

Volkan Kursun, Siva G. Narendra, Vivek K. De, Eby G. Friedman

Abstract—A low-voltage-swing MOSFET gate drive technique is proposed in this paper for enhancing the efficiency characteristics of high-frequency-switching dc–dc converters. The parasitic power...

Impedance Characteristics of Decoupling Capacitors in Multi-Power Distribution Systems (2004)

Sleep Switch Dual Threshold Voltage Domino Logic with Reduced Standby Leakage Current (2004)

To decrease power consumption without affecting circuit speed, multiple power supply voltages are often used in modern high performance ICs such as microprocessors. To maintain the impedance of a...

Volkan Kursun, Student Member, Eby G. Friedman

Abstract—A circuit technique is presented for reducing the subthreshold leakage energy consumption of domino logic circuits. Sleep switch transistors are proposed to place an idle dual threshold...

Analog Integrated Circuits and Signal Processing, 42, 231–238, 2005 c ○ 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands. Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages (2004)

Volkan Kursun, Siva G. Narendra, Vivek K. De, Eby G. Friedman

Abstract. A cascode bridge circuit for monolithic switching DC-DC converters operating at high input voltages is proposed in this paper. The proposed circuit can also be used as an I/O buffer to...

Dynamically Tuning Processor Resources with Adaptive Processing (2003)

Albonesi, David H., Balasubramonian, Rajeev, Dropsho, Steven, Dwarkadas, Sandhya, Friedman, Eby G., Huang, Michael C., ...

The productivity of modern society has become inextricably linked to its ability to produce energy-efficient computing technology. Increasingly sophisticated mobile computing systems, powered for...

Domino Logic with Variable Threshold Voltage Keeper (2003)

On the extraction of on-chip inductance (2003)

Abstract—A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of a keeper...

Reduced Delay Uncertainty in High Performance Clock Distribution Networks (2003)

Abstract-- Inductance extraction has become an important issue in the design of high speed CMOS circuits. Two characteristics of on-chip inductance are discussed in this paper that can significantly...

Dimitrios Velenis Marios, Marios C. Papaefthymiou, Eby G. Friedman

The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources, process parameter...

Managing Static Leakage Energy in Microprocessor Functional Units (2002)

Dropsho, Steven, Kursun, Volkan, Albonesi, David H., Dwarkadas, Sandhya, Friedman, Eby G.

Static energy due to subthreshold leakage current is projected to become a major component of the total energy in high performance microprocessors. Many studies so far have examined and proposed...

Managing static leakage energy in microprocessor functional units (2002)

Steven Dropsho, Volkan Kursun, David H. Albonesi, Hya Dwarkadas, Eby G. Friedman

Static energy due to subthreshold leakage current is projected to become a major component of the total energy in high performance microprocessors. Many studies so far have examined and proposed...

Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits (2002)

Roy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev

tbstract--This paper compares several methods for determining an optimal non-zero clock skew schedule for synchronous digital VLSI circuits. The optimality of a given dock skew schedule which...

c ○ World Scientific Publishing Company INDUCTANCE EFFECTS IN RLC TREES (2002)

Low Swing Dual Threshold Voltage Domino Logic (2002)

A closed form solution for characterizing voltage-based signals in an RLC tree is presented. The closed form solution is used to derive figures of merit to characterize the effects of inductance at a...

Properties of On-Chip Inductive Current Loops (2002)

A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active power consumption...

Andrey V. Mezhiba, Eby G. Friedman

The variation of inductance with circuit length is investigated in this paper. The nonlinear variation of inductance with length is shown to be a result of inductive coupling among circuit segments....

Efficiency Analysis of a High Frequency Buck Converter for On-Chip Integration with a Dual-VDD (2002)

Volkan Kursun, Siva G. Narendra, Vivek K. De, Eby G. Friedman

An analysis of the power characteristics of a buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and...

Optimizing Inductive Interconnect for Low Power (2002)

Retiming and Clock Scheduling for Digital Circuit Optimization (2002)

Abstract: The width of an interconnect line affects the total power consumed by a circuit. A trade off exists between the dynamic power and the short-circuit power dissipated in inductive...

Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman

This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimization problems are explored: (1)...

DTT: Direct Truncation of the Transfer Function - An Alternative to Moment Matching for Tree Structured Interconnect (2002)

Y. Ismail, Yehea I. Ismail, Eby G. Friedman

A method is introduced to evaluate time domain signals within RLC trees with arbitrary accuracy in response to any input signal. This method depends on finding a low frequency reduced-order transfer...

Repeater Insertion in Tree Structured Inductive Interconnect (2001)

Exploiting on-chip inductance in high speed clock distribution networks (2001)

Abstract-- The effects of inductance on repeater insertion in RLC trees is the focus of this paper. An algorithm is introduced to insert and size repeaters within an RLC tree to optimize a variety of...

Exploiting the on-chip inductance in high-speed clock distribution networks (2001)

Abstract On-chip inductance effects can be used to improve the performance of high speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually...

Repeater Insertion in Tree Structured Inductive Interconnect (2001)

Abstract—On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually...

Demonstration Of Power Enhancements On An Industrial Circuit (2001)

The effects of inductance on repeater insertion in trees is the focus of this paper. An algorithm is introduced to insert and size repeaters within an tree to optimize a variety of possible cost...

Through Delay Management, Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, ...

On-chip power dissipation has become a fundamental design issue in high performance integrated circuits. A technique to significantly reduce the power dissipated in the non-critical data paths of an...

Clock Distribution Networks in Synchronous Digital Integrated Circuits (2001)

Demonstration Of Speed Enhancements On An Industrial Circuit (2001)

this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the...

Through Application Of, Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, ...

A demonstration of the application of non-zero clock skew scheduling to enhance the speed characteristics of several functional unit blocks in a high performance processor is presented. It is shown...

c ○ World Scientific Publishing Company ON THE EXTRACTION OF ON-CHIP INDUCTANCE (2001)

A Clock Tree Topology Extraction Algorithm for Improving the Tolerance of Clock Distribution Networks to Delay Uncertainty (2001)

Inductance extraction has become an important issue in the design of high speed CMOS circuits. Two characteristics of on-chip inductance are discussed in this paper that can significantly simplify...

Dimitrios Velenis, Eby G. Friedman

The design of clock distribution networks in synchronous systems presents enormous challenges. Control of the clock signal delay in the presence of various noise sources, process parameter...

Repeater Insertion in Tree Structured Inductive Interconnect (2001)

Equivalent Elmore Delay for RLC Trees (2000)

Abstract – The effects of inductance on repeater insertion in RLC trees is the focus of this paper. An algorithm is introduced to insert and size repeaters within an RLC tree to optimize a variety...

Yehea I. Ismail, Eby G. Friedman, José L. Neves

Abstract—Closed-form solutions for the 50 % delay, rise time, overshoots, and settling time of signals in an tree are presented. These solutions have the same accuracy characteristics of the Elmore...

Demonstration of Speed and Power Enhancements through Application of Non-Zero Clock Skew Scheduling (2000)

Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman

Delay Uncertainty Due To On-Chip Simultaneous Switching Noise in High Performance CMOS Integrated circuits (2000)

Effects of inductance on the propagation delay and repeater insertion in VLSI circuits (2000)

Abstract – On-chip parasitic inductance inherent to the power supply rails has become significant in high speed digital circuits. Therefore, current surges result in voltage fluctuations within the...

Equivalent Elmore Delay for RLC Trees (2000)

Abstract- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5 % of dynamic circuit simulations for a wide range of RLC...

Equivalent Elmore Delay for RLC Trees (2000)

Abstract- Closed form solutions for the 50 % delay, rise time, overshoots, and settling time of signals in an RLC tree are presented. These solutions have the same accuracy characteristics of the...

Yehea I. Ismail, Eby G. Friedman, José L. Neves

Abstract—Closed-form solutions for the 50 % delay, rise time, overshoots, and settling time of signals in an tree are presented. These solutions have the same accuracy characteristics of the Elmore...

INTEGRATION, the VLSI journal 29 (2000) 131}165 (2000)

Delay And Noise, Kevin T. Tang, Eby G. Friedman

The e!ect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gate strongly depends upon the signal activity. A transient analysis of CMOS logic gates driving two...

2002 Kluwer Academic Publishers. Manufactured in The Netherlands. The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections (2000)

2002 Kluwer Academic Publishers. Manufactured in The Netherlands. Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates (2000)

Abstract. The effect of interconnect coupling capacitances on neighboring CMOS logic gates driving coupled interconnections strongly depends upon signal activity. A transient analysis of two...

Clock skew scheduling for improved reliability via quadratic programming (1999)

Abstract. Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and...

Ivan S. Kourtev, Eby G. Friedman

Abstract — This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadratic...

Interconnect Coupling Noise in CMOS VLSI Circuits (1999)

Interconnect Coupling Noise in CMOS VLSI Circuits (1999)

Abstract--Interconnect between a CMOS driver and re-ceiver can be modeled as a 1ossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or less than the time...

Clock skew scheduling for improved reliability via quadratic programming (1999)

Abstract--Interconnect between a CMOS driver and re-ceiver can be modeled as a 1ossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or less than the time...

Ivan S. Kourtev, Eby G. Friedman

Abstract — This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadratic...

Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits (1999)

Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman

This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths are considered,...

Maximizing Performance by Retiming and Clock Skew Scheduling (1999)

Xun Liu Marios, Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman

The application of retiming and clock skew scheduling for improving the operating speed of synchronous circuits under setup and hold constraints is investigated in this paper. It is shown that when...

Dynamic and short-circuit power of CMOS gates driving lossless transmission lines (1999)

Yehea I. Ismail, Eby G. Friedman, Senior Member, Jose Luis Neves

Abstract—The dynamic and short-circuit power consumption of a complementary metal–oxide–semidconductor (CMOS) gate driving an inductance–capacitance (LC) transmission line as a limiting case...

Tools for the Computer-Aided Design of Multigigahertz Superconducting Digital Circuits (1999)

Kris Gaj, Quentin P. Herr, Victor Adler, Andy Krasniewski, Eby G. Friedman, Marc J. Feldman

The realization of large integrated circuits depends upon the application of computer-aided design (CAD) tools. This paper summarizes the results of a survey of CAD tools targeting superconducting...

Noise immunity of digital circuits in mixed-signal smart power systems (1999)

Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, ...

Abstract | Experimental data describing circuit and physical design issues that in uence the noise immunity of digital latches in mixed-signal smart power circuits are described and discussed. The...

Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits (1999)

Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman

This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths are considered,...

A Performance On-Demand Approach to Power-Efficient Computing (1998)

Albonesi, David H., Dwarkadas, Sandhya, Friedman, Eby G., Scott, Michael L.

Complexity-Adaptive Processing (CAP) addresses increasing microprocessor power dissipation through on-the-fly, low-cost hardware adaptation and related circuit techniques so as to better match...

Figures of merit to characterize the importance of on-chip inductance (1998)

Figures of merit to characterize the importance of on-chip inductance (1998)

Abstract- A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer...

Optimum Repeater Insertion Based on a CMOS Delay Model for On-Chip RLC Interconnect (1998)

Abstract- A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer...

Retiming and Clock Scheduling for High-Performance Synchronous Circuits (1998)

A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 7% of SPICE simulations for a wide range of RLC loads. This expression is...

Marios C. Papaefthymiou, Eby G. Friedman, Xun Liu

This paper investigates retiming and clock skew scheduling for improving the performance of synchronous circuits. It is shown that when both long and short paths are considered, circuits optimized by...

Performance criteria for evaluating the importance of on-chip inductance (1998)

Yehea I. Ismail, Eby G. Friedman, Jose L. Nevesl

Two figures of merit are presented for determining whether a section of interconnect should be modeled as either an RL C or an R C impedance. The attenuation that a signal undergoes as it propagates...

Repeater Design to Reduce Delay and Power in Resistive Interconnect (1998)

Victor Adler, Student Member, Eby G. Friedman, Senior Member

Abstract—In large chips, the propagation delay of the data and clock signals can limit performance due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase...

Figures of merit to characterize the importance of on-chip inductance (1998)

Yehea I. Ismail, Eby G. Friedman, Senior Member, José L. Neves

Abstract — A closed-form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer...

Figures of merit to characterize the importance of on-chip inductance (1998)