Pulsed behavior of polymer protection devices (2009)
Bonfert, D., Gieser, H., Bock, K., Svasta, P., Ionescu, C.
Polymer protection devices are placed on circuit boards as chip devices to protect existing electronic devices from electrostatic discharge events (ESD). As there are no generally accepted standards...
Pulsed stress behavior of flexible thick film resistors (2008)
Bonfert, D., Wolf, H., Gieser, H., Klink, G., Bock, K., Svasta, P., ...
In order to investigate the behavior for very high current densities on polymer resistors on flexible substrates, a pulsed measurement technique was applied. The analytical test technique of...
Investigations with the capacitive coupled TLP on package and wafer-level (2007)
CDM is the major root cause for ESD failures in a modern production and test environment. CDM stress testing is well established for product qualification. Although specified as CDM failure voltage,...
Wolf, H., Gieser, H., Walter, D.
The method of the Capacitive Coupled Transmission Line Pulsing (CC-TLP) is applied to a product IC at package level and for the first time at wafer level. The investigated product showed a field...
Transmission line pulse stress on thick film resistors (2007)
Bonfert, D., Wolf, H., Gieser, H., Svasta, P., Romanescu, A., Cazacu, E.
One of the most important issues of resistors properties is the value stability under different electrical and non electrical influences. Mechanical and/or thermal stress together with the electrical...
Wolf, H., Gieser, H., Stadler, W., Wilkening, W., Rose, P., Qu, N.
This paper describes a test method which allows the investigation of the transient switching behavior of ESD-protection elements with very high transient resolution within the first nanoseconds. It...
ESD susceptibility of submicron air gaps (2006)
Wolf, H., Gieser, H., Bonfert, D., Hauser, M.
This work describes the investigation of the ESD susceptibility of submicron air gaps which are used e.g. in filter devices. The breakdown behaviour of the air gaps is analyzed in both the HBM (Human...
Transient-induced latch-up test setup for wafer-level and package-level (2006)
Bonfert, D., Gieser, H., Wolf, H., Frank, M., Konrad, A., Schulz, J.
Latch-up triggered by an impulse of short duration, is one root cause for field failures of CMOS devices. Standard tests. like JEDEC 78, which apply quasi-static overvoltage and overcurrent may fail...
ESD susceptibility of thick film chip resistors by means of transmission line pulsing (2006)
Bonfert, D., Wolf, H., Gieser, H., Stocker, A.
The change in resistance (dR) due to an applied high voltage pulse is a measure of the electrostatic discharge susceptibility of a resistor. The influence of the pulse width and height on the...
A dedicated TLP set-up to investigate the ESD robustness of RF elements and circuits (2005)
Wolf, H., Gieser, H., Soldner, W., Goßner, H.
This work describes the development of a combined RF-TLP test set-up. It alternates between pulsed high current characterization and scattering parameter measurements up to 10 GHz in order to...
Wolf, H., Gieser, H., Stadler, W., Wilkening, W.
This paper describes a new test method called capacitively coupled transmission line pulsing cc-TLP. It is applied to different test circuits which were mounted on specially designed package...
Transient latch-up: Experimental analysis and device simulation (2005)
Bargstädt-Franke, S., Stadler, W., Esmark, K., Streibl, M., Domanski, K., Gieser, H., ...
A set-up consisting of at least one pulse generator with baseline functionality was used for transient latch-up (TLU) investigations. Dependencies of the TLU sensitivity of test structures on the...
Test circuits for fast and reliable assessment of CDM robustness of I/O stages (2005)
Stadler, W., Esmark, K., Reynders, K., Zubeidat, M., Graf, M., Wilkening, W., ...
CDM hardening during the development of technology, devices, libraries and finally products differs significantly from the process well-established for HBM. This paper introduces a method on the...
Test circuits for fast and reliable assessment if CDM robustness of I/O stages (2005)
Esmark, K, Reynders, K, Zubeidat, M, Graf, M, Wilkening, W, ...
Characterization and modeling of transient device behavior under CDM ESD stress (2004)
Willemen, J., Andreini, A., Heyn, V. De, Esmark, K., Etherton, M., Gieser, H., ...
Very-fast high-current pulses that occur during charged device model (CDM) ESD events lead to transient voltage overshoots in forward- and reverse-biased pn-junctions, called forward recovery and...
Characterization and modeling of transient device behavior under CMD ESD stress (2004)
Andreini, A, De Heyn, Vincent, Esmark, K, Etherton, M, Gieser, H, ...
Bychikhin, S., Dubec, V., Litzenberger, M., Pogany, D., Gornik, E., Groos, G., ...
Switching dynamics and current flow homogeneity under very-fast TLP (vf-TLP) stress is investigated in smart power and CMOS technology ESD protection devices by means of optical transient...
Test circuits for fast and reliable assessment of CDM robustness of I/O stages (2003)
Esmark, K, Reynders, K, Zuhbeidat, M, Graf, M, Wilkening, W, ...
Characterization and modeling of transient device behavior under CDM ESD stress (2003)
Andreini, A, De Heyn, Vincent, Esmark, K, Etherton, M, Gieser, H, ...
Wolf, H., Gieser, H., Stadler, W., Esmark, K.
This paper describes the ESD circuit simulation of MOS transistors processed in a 0.18 µm CMOS technology. The extended model simulates the breakdown between the external base and the emitter...
NOVELTY - The device has a fixture (9,10) for a substrate (8) which contains one or several integrated circuits and structures to be charged. A pulse injector has a reference electrode (3) whose...
ESD in silicon integrated circuits (2002)
Anderson, W., Gieser, H., Ramaswamy, S.
Chapter Two introduces into phenomena of electrostatic discharge ESD which may damage integrated circuits. It discusses mechanisms generating the electrostatic voltage difference and the short...
Interchip Via Technology for Vertical System Integration (2001)
Ramm, P., Bonfert, D., Gieser, H., Haufe, J., Iberl, F., Klumpp, A., ...
Vertical System Integration(r) means the realization of three-dimensional integrated systems by thinning, stacking and vertical interchip wiring of completely processed and electrically tested device...
DE 19904751 C UPAB: 20000807 NOVELTY - A vertical IC, comprising a chip stack (30) with a via (25b) which electrically connects metallizations (4, 21) of spaced-apart chips (2, 19) and which is...
Characterization and optimization of a bipolar ESD-device by measurements and simulations (1999)
Stricker, A.D., Mettler, S., Wolf, H., Mergens, M., Wilkening, W., Gieser, H., ...
Investigation into socketed CDM (SDM) tester parasitics (1999)
Chaine, M., Verhaege, K., Avery, L., Kelly, M., Gieser, H., Bock, K., ...
Transient induced latch-up triggered by very fast pulses (1999)
The sensitivity of devices to latch-up triggered by short duration pulses is an often overlooked root cause for severe field failures. Standard JEDEC 17 tests applying quasi-static voltages and...
Egger, P., Gieser, H., Kropf, R., Guggenmos, X.
ESD-monitor circuits are introduced and used to evaluate failure mechanisms and susceptibilities with respect to the Charged Device Model. The performance of protection elements is studied by means...
Egger, P., Gieser, H., Kropf, R., Guggenmos, X.
ESD-monitor circuits are introduced and used to evaluate failure mechanisms and susceptibilities with respect to the Charged Device Model. The performance of protection elements is studied by means...
CDM-Testervergleich anhand eines Monitor-Schaltkreises (1995)
Egger, P., Kropf, R., Gieser, H., Guggenmos, X.
Die Erfahrung bei Entwicklung und Test von ESD-Schutzkonzepten für Integrierte Schaltungen zeigten komplexe Wechselwirkungen zwischen Schutzelement, zu schützender Schaltung, Technologie und dem...
Mußhoff, C., Wolf, H., Gieser, H.
Die Entwicklung und die Anwendung eines Rechteckimpulsgenerators für hohe Impulsströme ist Gegenstand dieses Beitrags. Die Impulse variabler Dauer werden mittels Transmission-Line und Relais...
Survey on electrostatic susceptibility of integrated circuits (1994)
From traditional assumptions and simplifications, different attitudes towards electrostatic discharges (ESD) in present microelectronics have been developed. The central question remains, which level...
ESD protection elements during HBM stress tests - further numerical and experimental results (1994)
Russ, C., Gieser, H., Verhaege, K.
Correlation problems for HBM-ESD testing result from the complex interaction between device and tester. The HBM stress of different wellcharacterized testers is applied to protection elements. By...
ESD protection elements during HBM stress tests - further numerical and experimental results (1994)
Russ, C., Gieser, H., Verhaege, K.
Correlation problems for HBM-ESD testing result from the complex interaction between device and tester. The HBM stress of different wellcharacterized testers is applied to protection elements. By...
Compact electro-thermal simulation of ESD-protection elements (1994)
Russ, C., Gieser, H., Egger, P., Irl, S.
Numerical simulations at the circuit level can improve the understanding of the behaviour of protection structures under system aspects. Full protection circuits with the influence of HBM ESD tester...
Analysis of HBM ESD testers and specifications using a fourth-order lumped element model (1994)
Verhaege, K., Roussel, P.J., Groeseneken, G., Maes, H.E., Gieser, H., Russ, C., ...
This paper presents the general and analytical solution of a fourth-order lumped element model (LEM) to describe human body model (HBM) electrostatic discharge (ESD) testers including the main tester...