Unified Incremental Physical-Level and High-Level Synthesis (2009)
Zhenyu Gu, Student Member, Jia Wang, Robert P. Dick, Hai Zhou, Senior Member
Abstract—Achieving design closure is one of the biggest challenges for modern very large-scale integration system designers. This problem is exacerbated by the lack of high-level designautomation...
Automatic Vulnerability Checking of IEEE 802.16 WiMAX Protocols through TLA+ (2009)
Prasad Narayana, Ruiming Chen, Yao Zhao, Yan Chen, Zhi (judy Fu, Hai Zhou
Abstract — Vulnerability analysis is indispensably the first step towards securing a network protocol, but currently remains mostly a best effort manual process with no completeness guarantee....
Timing Budgeting under Arbitrary Process Variations ∗ (2008)
Timing budgeting under process variations is an important step in a statistical optimization flow. We propose a novel formulation of the problem where budgets are statistical instead of deterministic...
Automatic Vulnerability Checking of IEEE 802.16 WiMAX Protocols through TLA+ (2008)
Prasad Narayana, Ruiming Chen, Yao Zhao, Yan Chen, Zhi (judy Fu, Hai Zhou
Abstract — Vulnerability analysis is indispensably the first step towards securing a network protocol, but currently remains mostly a best effort manual process with no completeness guarantee....
Statistical Timing Analysis With Coupling (2008)
Debjit Sinha, Hai Zhou, Senior Member
Abstract—As technology scales to smaller dimensions, increasing process variations and coupling induced delay variations make timing verification extremely challenging. In this paper, the authors...
Processing Rate Optimization by Sequential System Floorplanning ∗ (2008)
Jia Wang, Ping-chih Wu, Hai Zhou
The performance of a sequential system is usually measured by its frequency. However, with the appearance of global interconnects that require multiple clock periods to communicate, the throughput is...
Unified Incremental Physical-Level and High-Level Synthesis (2008)
Zhenyu Gu, Student Member, Jia Wang, Robert P. Dick, Hai Zhou, Senior Member
Abstract—Achieving design closure is one of the biggest challenges for modern very large-scale integration system designers. This problem is exacerbated by the lack of high-level designautomation...
Arindam Mallik, Student Member, Debjit Sinha, Prithviraj Banerjee, Hai Zhou, Senior Member
Abstract—The modern era of embedded system design is geared toward the design of low-power systems. One way to reduce power in an application-specified integrated circuit (ASIC) implementation is...
Abstract Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains ∗ (2008)
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full optimization...
Pingqiang Zhou, Yuchun Ma, Zhouyuan Li, Robert P. Dick, Li Shang, Hai Zhou, ...
Abstract — Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized during 3D...
Global Routing with Crosstalk Constraints (2008)
R. Dekker, Fault Modeling, Om Access, Hai Zhou, D. F. Wong
[11] A. Jee and F. Ferguson, “Carafe: An inductive fault analysis tool for
Debasish Das, Ahmed Shebaita, Yehea Ismail, Hai Zhou, Kip Killpack
This paper presents a predictive framework for accurate static timing analysis in UDSM VLSI circuits. As technology scales to smaller dimensions, coupling capacitances are becoming a critical factor...
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects (2008)
Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir Batterywala, Narendra V Shenoy, Hai Zhou
Abstract — This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic...
Short Papers Statistical Timing Verification for Transparently Latched Circuits (2008)
Abstract—High-performance integrated-circuit designs need to verify the clock schedules as they usually have level-sensitive latches for their speed. With process variations,the verification needs...
Exact Gate Decomposition for Low-Power Technology Mapping (2007)
With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In technology mapping,...
Hai Zhou, Vigyan Singhal, Adnan Aziz
This paper is about exploring the power of retiming and resynthesis. We show that there exists a pair of "sequentially equivalent " designs so that one cannot be obtained from...
A driving thrust of my research is my strong persuasion that practical and theoretical concerns are not mutually exclusive. I am most stimulated by problems of a practical motivation and try to...
Interconnect-Driven Floorplanning by Searching Alternative Packings (2007)
In traditional floorplanners, area minimization is an important issue. Due to the recent advances in VLSI technology, the number of transistors in a design and their switching speeds are increasing...
Fast min-cost buffer insertion under process variations (2007)
Process variation has become a critical problem in modern VLSI fabrication. In the presence of process variation, buffer insertion problem under performance constraints becomes more difficult since...
Advances in computation of the maximum of a set of random variables (2006)
Debjit Sinha, Hai Zhou, Narendra V. Shenoy
This paper quantifies the approximation error in Clark’s approach [1] to computing the maximum (max) of Gaussian random variables; a fundamental operation in statistical timing. We show that a...
Debjit Sinha, Hai Zhou, Debjit Sinha, Hai Zhou
This paper presents an approach to compute the tightness probabilities of Gaussian random variables with dynamic runtime-accuracy trade-off options. Tightness probabilities are required during the...
Yield-aware cache architectures (2006)
Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields have dropped to around...
A timing dependent power estimation framework considering coupling (2006)
Debjit Sinha, Diaaeldin Khalil, Yehea Ismail, Hai Zhou
In this paper, we propose a timing dependent dynamic power estimation framework that considers the impact of coupling and glitches. We show that relative switching activities and times of coupled...
A timing dependent power estimation framework considering coupling (2006)
Debjit Sinha, Diaaeldin Khalil, Yehea Ismail, Hai Zhou
In this paper, we propose a timing dependent dynamic power estimation framework that considers the impact of coupling and glitches. We show that relative switching activities and times of coupled...
FA-STAC: A framework for fast and accurate static timing analysis with coupling (2006)
Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea Ismail, Kip Killpack
Abstract — This paper presents a framework for fast and accurate static timing analysis considering coupling. With technology scaling to smaller dimensions, the impact of coupling induced delay...
Arindam Mallik, Debjit Sinha, Prith Banerjee, Hai Zhou
The modern era of embedded system design is geared towards design of low-power systems. One way to reduce power in an ASIC implementation is to reduce the bit-width precision of its computation...
A timing dependent power estimation framework considering coupling (2006)
Debjit Sinha, Diaaeldin Khalil, Yehea Ismail, Hai Zhou
In this paper, we propose a timing dependent dynamic power estimation framework that considers the impact of coupling and glitches. We show that relative switching activities and times of coupled...
Statistical timing yield optimization by gate sizing (2006)
Debjit Sinha, Narendra V. Shenoy, Hai Zhou, Senior Member, Senior Member
Abstract—In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling,...
Clustering for processing rate optimization (2005)
Chuan Lin, Jia Wang, Hai Zhou, Senior Member
Abstract—Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level may have...
Spanning Graph-based Nonrectilinear Steiner Tree Algorithms (2005)
Qi Zhu, Student Member, Hai Zhou, Senior Member, Tong Jing, Xian-long Hong, ...
Abstract—With advances in fabrication technology of very/ultra large scale integrated circuit (VLSI/ULSI), we must face many new challenges. One of them is the interconnect effects, which may cause...
Timing Yield Estimation Using Statistical Static Timing Analysis (2005)
Abstract—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for...
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk (2005)
Latches are extensively used in high-performance sequential circuit designs to achieve high frequencies because of their good performance and time borrowing feature. However, the amount of timing...
Incremental exploration of the combined physical and behavioral design space (2005)
Zhenyu (peter Gu, Jia Wang, Robert P. Dick, Hai Zhou
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly important factors such...
Wire retiming as fixpoint computation (2005)
Chuan Lin, Student Member, Hai Zhou, Senior Member
operation time is spent on global wires with long delays. Retiming–that is moving flip-flops in a circuit without changing its functionality–can be explored to pipeline long interconnect wires in...
Interconnect estimation without packing via ACG floorplans (2005)
Abstract — ACG (Adjacent Constraint Graph) is a general floorplan representation. The refinement of constraint graphs gives not only an efficient representation but also a representation sharing...
Optimal gate sizing for coupling-noise reduction (2004)
Coupling-noise reduction has emerged as a critical design problem with VLSI feature sizes shrinking rapidly and with the use of more aggressive and less noise-immune circuits. Since coupling-noise on...
Efficient octilinear steiner tree construction based on spanning graphs (2004)
Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang
Abstract--Octilinear interconnect is a promising technique to shorten wire lengths. We present two practical heuristic octilinear Steiner tree (OSMT) algorithms in the paper. They are both based on...
Clock schedule verification under process variations (2004)
With aggressive scaling down of feature sizes in VLSI fabrication, process variations have become a critical issue in designs, especially for high-performance ICs. Usually having level-sensitive...
Optimal wire retiming without binary search (2004)
Chuan Lin, Student Member, Hai Zhou, Senior Member
Abstract—The problem of retiming over a netlist of macroblocks to achieve minimal clock period, where block internal structures may not be changed and flip-flops may not be inserted on some wire...
Efficient octilinear steiner tree construction based on spanning graphs (2004)
Q. Zhu, H. Zhou, T. Jing, X. Hong, Y. Yang, Qi Zhu, ...
Abstract--Octilinear interconnect is a promising technique to shorten wire lengths. We present two practical heuristic octilinear Steiner tree (OSMT) algorithms in the paper. They are both based on...
Dedicated to my family. (2003)
Hung-ming Chen, Aloysius K. Mok, Donald S. Fussell, Mohamed G. Gouda, Xiaoping Tang, ...
I am greatly indebted to my dissertation advisor Professor Martin D.F. Wong for bringing me to the area of VLSI design automation. His guidance and encour-agement have been a tremendous assistance...
Major: Electronic Engineering HONORS AND AWARDS (2001)
Jia Wang, Advisor Professor, Hai Zhou
• Research on statistical analysis and optimization. • Research on the fundamentals of floorplanning. • Developed floorplanning techniques for power and thermal aware designs. • Research on...
Efficient minimum spanning tree construction without Delaunay triangulation (2001)
Without Delaunay Triangulation, Hai Zhou, Narendra Shenoy, William Nicholls
Minimum spanning tree problem is a very important problem in VLSI CAD. Given n points in a plane, a minimum spanning tree is a set of edges which connects all the points and has a minimum total...
Optimal low power xor gate decomposition (2000)
With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. For the problem of low...
Optimal low power xor gate decomposition (2000)
With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. For the problem of low...
Simultaneous routing and bu er insertion with restrictions on bu er Locations (1999)
Hai Zhou, D. F. Wong, I-min Liu, Adnan Aziz
During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid bu ers to be inserted. They give restrictions on bu er locations. In...
Integrated floorplanning and interconnect planning (1999)
Hung-ming Chen, Hai Zhou, D. F. Wong, Hannah H. Yang, Naveed Sherwani
The VLSI fabrication has entered the deep sub-micron era and communication between different components has significantly increased. Interconnect delay has become the dominant factor in total circuit...
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations (1999)
Hai Zhou, D. F. Wong, I-min Liu, Adnan Aziz
During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In...
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation (1999)
I-min Liu, Adnan Aziz, D. F. Wong, Hai Zhou
We propose a novel buffer insertion algorithm for handling more general networks, whose underlying topology is a directed acyclic graph rather than just a RC tree. The algorithm finds a global...
Integrated Floorplanning and Interconnect Planning (1999)
Hung-Ming Chen, Hai Zhou, F.Y. Young, D. F. Wong, Hannah H. Yang, Naveed Sherwani
When VLSI fabrication enters the deep sub-micron era, communication between different components is significantly increased. Interconnect delay also becomes the dominant factor in total circuit...
Global routing with crosstalk constraints (1998)
Due to the scaling down of device geometry and increasing frequency in deep sub-micron designs, crosstalk between interconnection wires has become an important issue in VLSI layout design. In this...
Global routing with crosstalk constraints (1998)
Due to the scaling down of device geometry and increasing frequency in deep sub-micron designs, crosstalk between interconnection wires has become an important issue in VLSI layout design. In this...
Buffer Minimization in Pass Transistor Logic (1998)
Hai Zhou, Synopsys Inc, Adnan Aziz
With the shrinking feature sizes and increasing transistor counts on chips, the push for higher speed and lower power makes it necessary to look for alternative design styles which offer better...
Simultaneous PTL Buffer Insertion and Sizing for Minimizing Elmore Delay (1998)
Min Liu, Tai-hung Liu, Hai Zhou, Adnan Aziz
For many digital designs, implementation in pass transistor logic (PTL) has been shown to be superior in terms of area, timing, and power characteristics to static CMOS. One problem with PTL circuits...
Buffer Minimization in Pass Transistor Logic (1998)
Since the technical limits of existing circuit families, such as static CMOS, alternative circuit families are pursued for the development of chips that can operate at speeds significantly above 500...
Buffer Minimization in Pass Transistor Logic (1998)
With the shrinking feature sizes and increasing transistor counts on chips, the push for higher speed and lower power makes it necessary to look for alternative design styles which offer better...
How Powerful is Retiming? (1998)
Hai Zhou, Vigyan Singhal, Adnan Aziz
This paper is about exploring the power of retiming and resynthesis. We show that there exists a pair of "sequentially equivalent" designs so that one cannot be obtained from another by a...
Global routing with crosstalk constraints (1998)
Due to the scaling down of device geometry and increasing frequency in deep sub-micron designs, crosstalk between interconnection wires has become an important issue in VLSI layout design. In this...
Optimal river routing with crosstalk constraints (1998)
With the increasing density of VLSI circuits, the interconnection wires are being packed even closer. This has increased the effect of interaction among these wires on circuit performance and hence,...
Crosstalk constrained maze routing based on Lagrangian relaxation (1997)
With the increasing density of VLSI circuits, interconnection wires are getting packed even closer. This has increased the effect of interaction between wires on circuit performance and hence, the...
An Exact Gate Decomposition Algorithm for Low-Power Technology Mapping (1997)
With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In technology mapping,...
Optimal non-uniform wire-sizing under the Elmore delay model (1996)
Chung-ping Chen, Hai Zhou, D. F. Wong
We consider non-uniform wire-sizing for general routing trees under the Elmore delay model. Three minimization objectives are studied: 1) total weighted sink-delays; 2) total area subject to...
An Optimal Algorithm for River Routing with Crosstalk Constraints (1996)
With the increasing density of VLSI circuits, the interconnection wires are getting packed even closer. This has increased the effect of interaction between these wires on circuit performance and...
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal
. The logic of equality with uninterpreted functions has been proposed for verifying abstract hardware designs. The ability to perform fast satisfiability checking over this logic is imperative for...
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions
Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal
. The logic of equality with uninterpreted functions has been proposed for verifying abstract hardware designs. The ability to perform fast satisfiability checking over this logic is imperative for...