with Hierarchical Searching and Shift Redundancy Architecture (2008)
Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Atsushi Amo, Atsushi Hachisuka, Hans Jürgen Mattausch, ...
Ternary CAMs (TCAMs) are becoming increasingly important for realizing networking applications such as address classification or packet filtering. Unfortunately, conventional static TCAMs have three...
Takashi Morimoto †a, Student Member, Tetsushi Koide, Hans Jürgen Mattausch
SUMMARY This letter presents a boundary-active-only (BAO) power reduction technique for cell-network-based region-growing video segmentation. The key approach is an adaptive situation-dependent power...
KUMAKI, Takeshi, ISHIZAKI, Masakatsu, KOIDE, Tetsushi, MATTAUSCH, Hans Jürgen, KURODA, Yasuto, GYOHTEN, Takayuki, ...
This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The...
JOHGUCHI, Koh, MATTAUSCH, Hans Jürgen, KOIDE, Tetsushi, HIRONAKA, Tetsuo
The presented unified data/instruction cache design uses multiple banks and features 4 ports, distributed crossbar, different word-length for data and instruction ports, interleaved cache-line words...
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor (2007)
KUMAKI, Takeshi, ISHIZAKI, Masakatsu, KOIDE, Tetsushi, MATTAUSCH, Hans Jürgen, KURODA, Yasuto, NODA, Hideyuki, ...
This paper reports an efficient Discrete Cosine Transform (DCT) processing method for images using a massive-parallel memory-embedded SIMD matrix processor. The matrix-processing engine has 2,048...
Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories (2007)
ABEDIN, Md. Anwarul, TANAKA, Yuki, AHMADI, Ali, SAKAKIBARA, Shogo, KOIDE, Tetsushi, MATTAUSCH, Hans Jürgen
The realization of k-nearest-matches search capability in fully-parallel mixed digital-analog associative memories by a sequential autonomous search mode is reported. The proposed concept and circuit...
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer (2007)
KUMAKI, Takeshi, KURODA, Yasuto, ISHIZAKI, Masakatsu, KOIDE, Tetsushi, MATTAUSCH, Hans Jürgen, NODA, Hideyuki, ...
This paper presents a novel optimized real-time Huffman encoder using a pipelined data path based on CAM technology and a parallel code-word-table optimizer. The exploitation of CAM technology...
KUMAKI, Takeshi, KONO, Yutaka, ISHIZAKI, Masakatsu, KOIDE, Tetsushi, MATTAUSCH, Hans Jürgen
This paper presents a scalable FPGA/ASIC implementation architecture for high-speed parallel table-lookup-coding using multi-ported content addressable memory, aiming at facilitating effective...
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC (2006)
NODA, Hideyuki, DOSAKA, Katsumi, MATTAUSCH, Hans Jürgen, KOIDE, Tetsushi, MORISHITA, Fukashi, ARIMOTO, Kazutami
This paper describes a novel TCAM architecture designed for enhancing the soft-error immunity. An associated embedded DRAM and ECC circuits are placed next to TCAM macro to implement a unique...
Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation (2006)
MORIMOTO, Takashi, ADACHI, Hidekazu, KIRIYAMA, Osamu, KOIDE, Tetsushi, MATTAUSCH, Hans Jürgen
This letter presents a boundary-active-only (BAO) power reduction technique for cell-network-based region-growing video segmentation. The key approach is an adaptive situation-dependent power...
1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation (2005)
MATSUMOTO, Shizunori, UENO, Hiroaki, HOSOKAWA, Satoshi, KITAMURA, Toshihiko, MIURA-MATTAUSCH, Mitiko, MATTAUSCH, Hans Jürgen, ...
A systematic experimental and modeling study is reported, which characterizes the low-frequency noise spectrum of 100 nm-MOSFETs accurately. Two kinds of measured spectra are observed: 1/f and...
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh (2005)
NODA, Hideyuki, INOUE, Kazunari, MATTAUSCH, Hans Jürgen, KOIDE, Tetsushi, DOSAKA, Katsumi, ARIMOTO, Kazutami, ...
This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme....
A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential (2005)
NAVARRO, Dondee, MIZOGUCHI, Takeshi, SUETAKE, Masami, HISAMITSU, Kazuya, UENO, Hiroaki, MIURA-MATTAUSCH, Mitiko, ...
We have developed a model for circuit-simulation which describes the MOSFET region from pinch-off to drain contact based on the surface potential. The model relates the surface-potential increase...
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features (2005)
INOUE, Kazunari, NODA, Hideyuki, ARIMOTO, Kazutami, MATTAUSCH, HANS Jürgen, KOIDE, Tetsushi
A signature-matching co-processor in 130 nm CMOS technology for application in the network-security field is presented. Two key search technologies, implemented with fully-parallel CAM-based search...
Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch
Abstract- We designed a cell-network-based full-custom testchip for gray-scale/color image segmentation of real-time videosignals in 350nm CMOS technology. From this digital test-chip design,...
A novel hierarchical multi-port cache (2003)
Zhaomin Zhu, Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide
A novel hierarchical multi-port cache is described in this paper, which implements the Hierarchical Multi-port memory Architecture (HMA) based on 1-port banks. This type of cache has the advantages...