A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding (2009)
Witte, Ernst Martin, Borlenghi, Filippo, Ascheid, Gerd, Leupers, Rainer, Meyr, Heinrich
Multiple-input multiple-output (MIMO) wireless transmission imposes huge challenges on the design of efficient hardware architectures for iterative receivers. A major challenge is soft-input...
Efficient And Portable SDR Waveform Development: The Nucleus Concept (2009)
Ramakrishnan, Venkatesh, Witte, Ernst M., Kempf, Torsten, Kammler, David, Ascheid, Gerd, Meyr, Heinrich, ...
Future wireless communication systems should be flexible to support different waveforms (WFs) and be cognitive to sense the environment and tune themselves. This has lead to tremendous interest in...
ON THE INTERACTION BETWEEN DSP-ALGORITH MS AND VLSI-ARCH ITECTURE ABSTRACT (2009)
Gerhard Fettweis, Heinrich Meyr
The evolving field of ASIC design enables the customized implementation of DSP-algorithms on dedicated chips. It therefore on the one hand opens up a number of new pos-sibilities, on the other hand...
ASIP Architecture Exploration for efficient IPSec Encryption: A Case Study (2008)
Hanno Scharwaechter, David Kammler, Andreas Wieferink, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, ...
Abstract. Application Specific Instruction Processors (ASIPs) are increasingly becoming popular in the world of customized, applicationdriven System-on-Chip (SoC) designs. Efficient ASIP design...
C Compiler Aided Design of Application-Specific Instruction-Set Processors Using (2008)
Von Fakultät, Elektrotechnik Informationstechnik, Oliver Wahlen, Dr. Rainer Leupers, ...
Die Deutsche Bibliothek lists this publication in the Deutsche Nationalbibliografie; detailed bibliographic data is available in the internet at
Analytical Bit Error Rate Calculation for BICM(-ID) Assuming Imperfect CSI (2008)
Susanne Godtmann, I-wei Lai, Tzi-dar Chiueh, Gerd Ascheid, Heinrich Meyr
Abstract—In this paper, we analytically derive the bit error rate (BER) for bit-interleaved coded modulation (BICM) under the assumption of a temporal correlated flat Rayleigh fading channel. We...
aus Vittorio Veneto, Italien (2008)
Von Fakultät, Elektrotechnik Informationstechnik, Nicola Da Dalt, ...
Summary In this thesis the theory and implementation of a digital bang-bang frequency synthesizer for application in the field of high speed serial data communications systems is presented. The...
Andreas Wieferink, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel
Current and future SoC designs will contain an increasing number of heterogeneous programmable units combined with a complex communication architecture to meet flexibility, performance and cost...
ABSTRACT Retargetable Generation of TLM Bus Interfaces for MP-SoC Platforms (2008)
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cores combined with a...
Jens Baltersee, Gunnar Fock, Heinrich Meyr
Abstract—The constrained capacity of a coherent coded modulation (CM) digital communication system with data-aided channel estimation and a discrete, equiprobable symbol alphabet is derived under...
A Code-Generator Generator for Multi-Output Instructions (2008)
Hanno Scharwaechter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very common in the area of...
ABSTRACT A Fast and Generic Hybrid Simulation Approach Using C Virtual Machine (2008)
Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Instruction Set Simulators (ISSes) are important tools for cross-platform software development. The simulation speed is a major concern and many approaches have been proposed to improve the...
Chapter 24 CORDIC Algorithms and Architectures (2008)
Digital signal processing (DSP) algorithms exhibit an increasing need for the e cient implementation of complex arithmetic operations. The computation of trigonometric functions, coordinate...
Lars Schmitt, Volker Simon, Thomas Grundler, Christoph Schreyoegg, Heinrich Meyr
Abstract — An analytical evaluation of the performance in terms of detection probability and mean detection time of a noncoherent detector at the base station is presented for a wideband CDMA...
A Wireless Revenue Based Scheduler with QoS Support (2008)
Andreas Senst, Peter Schulz-rittich, Daniel Croonen, Gerd Ascheid, Heinrich Meyr
We propose a revenue based scheduling approach for a time slotted wireless communications system that takes Quality-of-Service (QoS) requirements such as a certain minimum data rate, maximum bit...
A Rake Finger Grid for asynchronous DS-CDMA Systems using LMMSE Tap Weight Estimation (2008)
Volker Simon, Lars Schmitt, Thomas Grundler, Christoph Schreyögg, Heinrich Meyr
Abstract—In this paper a Rake finger grid structure for direct-sequence code division multiple access (DS-CDMA) systems is analyzed as an alternative to the conventional Rake structure using...
Peter Schulz-rittich, Andreas Senst, Thomas Bilke, Heinrich Meyr
Abstract — We analyze a cellular communication system in which a basestation (BTS) or access point transmits packet data to several mobile data users by means of a TDMA scheme. All users estimate...
ARQ Protocol Performance for a Wireless High Data Rate Link (2007)
Uwe Lambrette, Lars Brühl, Heinrich Meyr
In order to determine the performance of wireless data transmssion at high data rates consideration of channel transmission characteristics, intersymbol interference reduction (equalization) channel...
A Digital Feedforward Differential Detection MSK Receiver for Packet-Based Mobile Radio (2007)
: - We present a differential MSK receiver with coarse frame synchronization using a RSSI Signal and thus allowing the use of the capture phenomenon. The capture event is detected by an ML--derived...
Comparison of Demodulation Techniques for MSK (2007)
Uwe Lambrette, Ralf Mehlan, Heinrich Meyr
. For MSK, three demodulators are compared. The first demodulation algorithm, partially coherent demodulation, is based on a classical matched filter approach combined with feedforward phase...
Viterbi Decoding with Dual Timescale Traceback Processing (2007)
Olaf J. Joeressen, Heinrich Meyr
In this paper a new approach to traceback processing in Viterbi decoders is presented. The approach reduces memory requirements as compared to previous approaches by using different speeds during...
ABSTRACT A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation (2007)
Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann
In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance is a key factor for...
Code Generation and Optimziation Techniques for Embedded Digital Signal Processors (2007)
Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang, Guido Araujo, ...
The advent of 0.5 processing that allows for the integration of 5 million transistors on a single integrated circuit has brought forth new challenges and opportunities in embedded-system design. This...
Tilman Gl Okler, Stefan Bitterlich, Heinrich Meyr
A design methodology is presented to optimize application specific instruction set processors (ASIPs) with respect to performance and power. The methodology uses semi-custom design with incremental...
DSP CORE VERIFICATION USING AUTOMATIC TEST CASE GENERATION (2007)
Tilman Glokler, Stefan Bitterlich, Heinrich Meyr
The verification methodology for a TMS320C25 compatible embedded DSP core is described. The DSP core has been implemented in synthesizable VHDL and has been cosimulated with the original DSP to...
Tilman Gl Okler, Stefan Bitterlich, Heinrich Meyr
Application specific instruction set processors (ASIPs) can be optimized both for speed and power taking advantage of the flexibility of a synthesized semi-custom implementation. The current case...
ASIP Design and the Energy-Flexibility Tradeo (2007)
Modern standards and applications demand a large degree of exibility and congurability for state of the art electronic devices. One example for this exibility is the UMTS standard which enables...
INTEGER CODE GENERATION FOR THE TI TMS320C62X (2007)
Martin Coors, Holger Keding, Olaf Lüthje, Heinrich Meyr
This paper presents a methodology which enables the generation of C62x optimized fixed-point C-code from a floating-point description of an algorithm. The FRIDGE design environment transforms...
Peter Schulz-rittich, Andreas Senst, Thomas Bilke, Heinrich Meyr
Abstract--- We analyze a cellular communication system in which a basestation (BTS) or access point transmits packet data to several mobile data users by means of a TDMA scheme. All users estimate...
Exploring the UMTS WCDMA-Receiver Design Space Using a Semianalytical Approach (2007)
Gunnar Fock, Jens Baltersee, Peter Schulz-Rittich, Heinrich Meyr
A fast simulation technique for the analysis of the system performance of digital receivers is presented and applied to the UMTS terrestrial radio access (UTRA). This semianalytical method comprises...
Manuel Hohenauer, Hanno Scharwaechter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, ...
Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based on LISA, an...
On the Influence of Pilot Symbol and Data Symbol Positioning on Turbo synchronization (2007)
Godtmann, Susanne, Pollok, Andre, Hadaschik, Niels, Ascheid, Gerd, Meyr, Heinrich
Iterative Code-Aided Phase Noise Synchronization Based on the LMMSE Criterion (2007)
Pollok, Andre, Godtmann, Susanne, Hadaschik, Niels, Ascheid, Gerd, Meyr, Heinrich
On the influence of pilot symbol and data symbol positioning on turbo synchronization (2007)
Godtmann, Susanne, Pollok, Andre, Hadaschik, Niels, Ascheid, Gerd, Meyr, Heinrich
Iterative Code-Aided Phase Noise Synchronization Based on the LMMSE Criterion (2007)
Pollok, Andre, Godtmann, Susanne, Hadaschik, Niels, Ascheid, Gerd, Meyr, Heinrich
On the influence of pilot symbol and data symbol positioning on turbo synchronization (2007)
Godtmann, Susanne, Pollok, Andre, Hadaschik, Niels, Ascheid, Gerd, Meyr, Heinrich
Design and implementation of a modular and portable ieee 754 compliant floating-point unit (2006)
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Multimedia and communication algorithms from embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-point hardware, final...
Integrated Verification Approach during ADL-Driven Processor Design (2006)
Anupam Chattopadhyay, Arnab Sinha, David Kammler, Ian Zhang, Rainer Leupers, Heinrich Meyr
Nowadays, Architecture Description Languages (ADLs) are getting popular to achieve quick and optimal design convergence during the development of Application Specific Instruction-Set Processors...
Coarse and Turbo Synchronization: A Case-Study for DVB-RCS (2006)
Godtmann, Susanne, Hadaschik, Niels, Steinert, Wolfgang, Pollok, Andre, Ascheid, Gerd, Meyr, Heinrich
Coarse and Turbo Synchronization: A Case-Study for DVB-RCS (2006)
Godtmann, Susanne, Hadaschik, Niels, Steinert, Wolfgang, Pollok, Andre, Ascheid, Gerd, Meyr, Heinrich
C Compiler Retargeting Based on Instruction Semantics Models (2005)
Ceng, Jianjiang, Hohenauer, Manuel, Leupers, Rainer, Ascheid, Gerd, Meyr, Heinrich, Braun, Gunnar
Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compilers that can be...
C Compiler Retargeting Based on Instruction Semantics Models (2005)
Ceng, Jianjiang, Hohenauer, Manuel, Leupers, Rainer, Ascheid, Gerd, Meyr, Heinrich, Braun, Gunnar
Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compilers that can be...
C compiler retargeting based on instruction semantics models (2005)
Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compilers that can be...
Fine-grained application source code profiling for ASIP design (2005)
Kingshuk Karuri, Mohammad Abdullah, Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, ...
Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Languages (ADLs) and...
C compiler retargeting based on instruction semantics models (2005)
Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compilers that can be...
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models (2004)
Manuel Hohenauer, Hanno Scharwaechter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, ...
Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based on LISA, an...
Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Current and future SoC designs will contain an increasing number of heterogeneous programmable units combined with a complex communication architecture to meet flexibility, performance and cost...
Early iss integration into network-on-chip designs (2004)
Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Abstract. Future signal processing SoC designs will contain an increasing number of heterogeneous programmable units combined with a complex communication architecture to meet flexibility,...
Processor/memory co-exploration on multiple abstraction levels (2003)
Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr
Recently, the evolution of embedded systems has shown a strong trend towards application-specific, single-chip solutions. As a result, application-specific instruction set processors (ASIP) are more...
Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prevent time consuming...
Tim Kogel, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Abstract — The ever increasing complexity and heterogeneity of modern System-on-Chip designs demands early consideration and exploration of architectural alternatives, which is hardly practicable...
A Wireless Revenue Based Scheduler with QoS Support (2003)
Andreas Senst, Peter Schulz-Rittich, Daniel Croonen, Gerd Ascheid, Heinrich Meyr
We propose a revenue based scheduling approach for a time slotted wireless communications system that takes Quality-of-Service (QoS) requirements such as a certain minimum data rate, maximum bit...
A Generic Tool-Set for SoC Multiprocessor Debugging and Synchronization (2003)
Andreas Wieferink, Tim Kogel, Rainer Leupers, Heinrich Meyr, Achim Nohl, Andreas Hoffmann
Current and future SoC designs will contain an increasing number of programmable units. To be able to tailor and debug these processors in their system context at the highest possible overall...
Peter Schulz-rittich, Andreas Senst, Ulrich Krause, Heinrich Meyr
Abstract — We analyze a cellular communication system in which a basestation or access point equipped with several antennas transmits packet data to several mobile data users by means of a TDMA...
Andreas Senst, Ulrich Krause, Heinrich Meyr
We analyze a cellular communication system in which a basestation or access point equipped with several antennas transmits packet data to several mobile data users by means of a TDMA scheme. A...
Design and DSP Implementation of Fixed-Point Systems (2002)
Martin Coors, Holger Keding, Olaf Lüthje, Heinrich Meyr
This article is an introduction to the FRIDGE design environment which supports the design and DSP implementation of fixed-point digital signal processing systems. We present the tool-supported...
Low Complexity High Resolution Subspace-Based Delay Estimation for DS-CDMA (2002)
Gunnar Fock, Peter Schulz-rittich, Andreas Schenke, Heinrich Meyr
Abstract--- In this paper we consider the problem of estimating the propagation delays of a synchronous directsequence code division multiple access (DS-CDMA) system operating over a multipath fading...
Von Fakultät, Elektrotechnik Informationstechnik, Aus Aachen, Dr. Heinrich Meyr
Diese Dissertation ist auf den Internetseiten der Hochschulbibliothek online verfügbar. Vorwort
Design and DSP Implementation of Fixed-Point Systems (2002)
Heinrich Meyr, Olaf Lüthje, Holger Keding, Martin Coors
This article is an introduction to the FRIDGE design environment which supports the design and DSP implementation of fixed-point digital signal processing systems. We present the tool-supported...
Design and DSP Implementation of Fixed-Point Systems (2002)
Martin Coors, Holger Keding, Olaf Lüthje, Heinrich Meyr
This article is an introduction to the FRIDGE design environment which supports the design and DSP implementation of fixed-point digital signal processing systems. We present the tool-supported...
A survey on modeling issues using the machine description language LISA (2001)
Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr
This paper presents a survey on modeling issues of programmable architectures using the machine description language LISA. Various architectures presenting diverse architectural characteristics will...
Generating production quality software development tools using a machine description language (2001)
Andreas Hoffmann, Achim Nohl, Stefan Pees, Gunnar Braun, Heinrich Meyr
This paper presents a methodology to automatically generate production quality software development tools for programmable architectures using the machine description language LISA. Various...
A framework for fast hardware-software co-simulation (2001)
Andreas Hoffmann, Tim Kogel, Heinrich Meyr
We present a new hardware-software co-simulation framework enabling fast prototyping in system-on-chip designs. On the software side, the machine description language LISA allows the generation of...
Gunnar Braun, Andreas Hoffmann, Achim Nohl, Heinrich Meyr
Instruction set simulators are indispensable tools for both the design of programmable architectures and software development. However, due to a constantly increasing processor complexity and the...
Power reduction for ASIPs: A case study (2001)
Abstract- Application specific instruction set processors (ASIPs) are an excellent architecture for mixed control/data-flow oriented tasks with medium to low data rate and high complexity. The main...
Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, ...
The development of application-specific instruction -set processors (ASIP) is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such...
Peter Schulz-rittich, Gunnar Fock, Jens Baltersee, Heinrich Meyr
Abstract--- A new adaptive timing error detector (TED) embedded in a code-tracking loop for RAKE reception of directsequence-CDMA signals is presented. The loop consists of a digital coherent TED and...
Stefan Pees, Andreas Hoffmann, Heinrich Meyr
This paper presents a methodology to retarget the technique of compiled simulation for Digital Signal Processors (DSPs) using the modeling language LISA. In the past, the principle of compiled...
Retargetable compiled simulation of embedded processors using a machine description language (2000)
Stefan Pees, Andreas Hoffmann, Heinrich Meyr
Fast processor simulators are needed for the software development ofembedded processors, for HW/SW cosimulation systems and for profiling and design of application specific processors. Such fast...
Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, Heinrich Meyr
This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation description, the architectural details...
FRIDGE: A Fixed-Point Design and Simulation Environment (1998)
Holger Keding Markus, Markus Willems, Martin Coors, Heinrich Meyr
Digital systems, especially those for mobile applications are sensitive to power consumption, chip size and costs. Therefore they are realized using fixed-point architectures, either dedicated HW or...
System Level Fixed-Point Design Based on an Interpolative Approach (1997)
Markus Willems, Holger Keding, Heinrich Meyr
The design process for �xed�point implementations either in software or in hardware requires a bit�true speci�cation of the algorithm in order to analyze quantization e�ects on an...
An Upper Bound Of The Throughput Of Multirate Multiprocessor Schedules (1997)
Rainer Schoenen, Vojin Zivojnovic, Heinrich Meyr, Zivojnovi'c Heinrich Meyr
Multirate Dataflow Graphs (MR-DFGs) are used for modelling iterative computations, allowing concurrency and arbitrary data rates at ports. This model is often used for signal processing algorithms....
Techniques for Frame Synchronization on Unknown Frequency Selective Channels (1997)
Uwe Lambrette, Jens Horstmannshoff, Heinrich Meyr
For burst oriented data transmission over frequency selective fading channels, the problem of optimum frame synchronization is discussed. A new criterion for frame synchronization accuracy is...
On Core and More: A Design Perspective for Systems-on-a-Chip (1997)
Stefan Pees, Martin Vaupel, Vojin Zivojnovic, Heinrich Meyr, Martin Vaupel Vojin, Zivojnovi'c Heinrich Meyr
In this survey, key drivers in design methodology are provided that enable successful design of systems-on-a-chip for the highly competitive telecommunications market. Main components of a design...
Uwe Lambrette, Stefan Fechtel, Heinrich Meyr
Modeling of the mobile radio channel is considered. Starting from a physical model, a frequency domain description of the channel is obtained. It is then shown that the effect of fading and...
OFDM Burst Frequency Synchronization by Single Carrier Training Data (1997)
Uwe Lambrette, Michael Speth, Heinrich Meyr
In this paper, we propose a burst frequency synchronization procedure which is based on the usage of single--carrier training data and OFDM payload modulation. The payload modulation format is...
Fast Simulation of the TI TMS320C54x DSP (1997)
Stefan Pees, Vojin Zivojnovic, Andreas Ropers, Heinrich Meyr
In this paper a new technique for fast simulation of pipelined digital signal processors (DSPs) is presented. In contrast to the existing timed and untimed instruction set simulators which use the...
Frame synchronization of OFDM systems in frequency selective fading channels (1997)
Michael Speth, Ferdinand Classen, Heinrich Meyr
This paper investigates the topic of frame synchronization for systems based on the OFDM principle. After introducing the system model we discuss the task of framesynchronization and analyze the...
DSP Processor/Compiler Co-Design: A Quantitative Approach (1996)
Vojin Zivojnovic, Stefan Pees, Christian Schläger, Markus Willems, Rainer Schoenen, Heinrich Meyr
In the paper the problem of processor/compiler codesign for digital signal processing and embedded systems is discussed. The main principle we follow is the top-down approach characterized by...
LISA - Machine Description Language and Generic Machine Model for HW/SW Co-Design (1996)
Vojin Zivojnovic, Stefan Pees, Heinrich Meyr
In the paper a new machine description language is presented. The new language LISA, and its generic machine model are able to produce bit- and cycle/phase-accurate processor models covering the...
A CMOS IC for Gb/s viterbi decoding: system design and VLSI implementation (1996)
Herbert Dawid, Student Member, Gerhard Fettweis, Heinrich Meyr
used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD’s) is limited by the inherent nonlinear add-compare-select (ACS) recursion....
COSSAP-MATLAB Cosimulation (1995)
Uwe Lambrette, Bernd Schmandt, Guido Post, Heinrich Meyr
In this contribution we describe the use and implementation of a new tool allowing the joint simulation of MATLAB and COSSAP 1 routines. In order to achieve this, the MATLAB simulation process is...
Compiled Simulation of Programmable DSP Architectures (1995)
Vojin Zivojnovic, Steven Tjiang, Heinrich Meyr
This paper presents a technique for simulating processors based on the principle of compiled simulation. Unlike existing, commercially available instruction set simulators for DSPs, which are of...
Rapid Prototyping of a DMSK Transceiver (1995)
Uwe Lambrette, Peter Zepter, Ralf Mehlan, Heinrich Meyr
this paper. For each data flow block in the data flow library that can be used for implementation (i.e. which is a possible component of a digital transmitter or receiver) there is at least one...
Code Generation And Optimization Techniques For Embedded Digital Signal Processors (1995)
Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang, Guido Araujo, ...
Introduction The advent of 0.5¯ processing that allows for the integration of 5 million transistors on a single integrated circuit has brought forth new challenges and opportunities in...
Two Timing Recovery Algorithms for MSK (1994)
We suggest two algorithms that allow efficient timing recovery for MSK based on the computation of the Fourier spectrum of the absolute value of the differential phases. One is suited for parallel...
Untersuchung korrelativer Trackingsysteme mit Hilfe der Fokker-Planck-Methode. (1974)
Diss. Nr. 5223 techn. Wiss. ETH Zürich 1974. (KA).