Interconnection Network and Distributed Shared Memory of a Massively Parallel Machine JUMP-1 (2007)
Hideharu Amano, Katsunobu Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Ken'ichiro Anjo
For cache coherent distributed shared memory on a large scale parallel machine, each node processor of JUMP-1 shares a global virtual address space with two-stage TLB implementation. The directory is...
Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic (2006)
OKUNO, Michitaka, NISHIMURA, Shinji, ISHIDA, Shin-ichi, NISHI, Hiroaki
A novel cache-based network processor (NP) architecture that can catch up with next generation 100-Gbps packet-processing throughput by exploiting a nature of network traffic is proposed, and the...
100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet (2006)
TOYODA, Hidehiro, NISHIMURA, Shinji, OKUNO, Michitaka, FUKUDA, Kouji, NAKAHARA, Kouji, NISHI, Hiroaki
A high-speed physical-layer architecture for Ethernet is described that supports 100-Gb/s throughput and 40-km transmission, making it well suited for next-generation metro-area and intrabuilding...
OKUNO, Michitaka, ISHIDA, Shin-ichi, NISHI, Hiroaki
A novel cache-based packet-processing-engine (PPE) architecture that achieves low-power consumption and high packet-processing throughput by exploiting the nature of network traffic is proposed. This...
3自由度モデルヘリコプタに対するパラメータ同定を伴う非干渉制御(機械力学,計測,自動制御) (2004)
石飛, 光章, 木下, 博, 西, 寛聡, イシトビ, ミツアキ, キノシタ, ヒロシ, ニシ, ヒロアキ, ...
This paper considers decoupling control of a model helicopter with three degree-of-freedom. Since its position control system is not decouplable via static-state feedback, we try to apply...
The RDT Router Chip: A versatile router for supporting a distributed shared memory (1997)
Hiroaki Nishi, Ken-ichiro Anjo, Tomohiro Kudoh, Hideharu Amano
Introduction JUMP-1 is a massively parallel processor prototype developed by a collaboration between seven Japanese universities [4]. The major goal of this project is to establish techniques for...