Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
Fat H-Tree is a novel tree-based interconnection network providing a torus structure, which is formed by combining two folded H-Tree networks, and is an attractive alternative to tree-based networks...
A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks (2009)
Various types of Networks-on-Chips (NoCs) have been employed light-weight routers compared with those in parallel computers, and a virtual-channel mechanism, which requires additional logic and...
Performance Oriented Management System for Reconfigurable Network Appliances (2008)
Hiroki Matsutani, Ryuji Wakikawa, Koshiro Mitsuya, Jun Murai
In this research, a performance oriented management system for network appliances is proposed to optimize the utilization of its hardware resources according to its environment at any time. This...
A Parametric Study of Scalable Interconnects on FPGAs (2008)
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano
Abstract — With the constantly increasing gate capacity of FP-GAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, Network-On-Chip...
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs (2007)
WANG, Daihan, MATSUTANI, Hiroki, KOIBUCHI, Michihiro, AMANO, Hideharu
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware...
Non-Minimal Routing Strategy for Application-Specific Networks-onChips (2005)
Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano
We propose a deterministic routing strategy called flee which introduces non-minimal paths in order to distribute traffic with a high degree of communication locality in Networks-on-Chips. In the...