Ricky Yuen, Marcus Van Ierssel, Ali Sheikholeslami, William W. Walker, Hirotaka Tamura
Abstract- We present a 5Gb/s transmitter that cancels the reflected signals from any impedance discontinuity located at up i out to 64U1I away from the transmitter and spread over 8U1 interval. T+...
A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance (2008)
Marcus Van Ierssel, Ali Sheikholeslami, Senior Member, Hirotaka Tamura, William W. Walker
Abstract—A hybrid CDR is presented that embeds a 5 blind-oversampling CDR within a conventional phase-tracking CDR. This hybrid CDR has a jitter tolerance that is the product of the individual...
18.5 A 3.2Gb/s Semi-Blind-Oversampling CDR (2008)
Marcus Van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker
A blind-oversampling CDR tracks the high-frequency jitter of the input data stream, but is limited at low-frequencies by the size of its FIFO [1]. A phase-tracking CDR, on the other hand, tracks...
18-GHz Clock Distribution Using a Coupled VCO Array (2007)
SHIBASAKI, Takayuki, TAMURA, Hirotaka, KANDA, Kouichi, YAMAGUCHI, Hisakatsu, OGAWA, Junji, KURODA, Tadahiro
This paper describes an 18-GHz coupled VCO array for low jitter and low phase deviation clock distribution. To reduce the skew, jitter and power consumption associated with clock distribution, the...
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies (2006)
TAMURA, Hirotaka, KIBUNE, Masaya, YAMAGUCHI, Hisakatsu, KANDA, Kouichi, GOTOH, Kohtaroh, ISHIDA, Hideki, ...
The paper provides an overview of the circuit techniques for CMOS high-speed I/Os, focusing on the design issues in sub-100 nm standard CMOS. First, we describe the evolution of CMOS high-speed I/O...
PROPOSAL OF SINGLE-FLUX-QUANTUM LOGIC DEVICE (1980)
Tamura, Hirotaka, Okabe, Yoichi, Sugano, Takuo
A new type of logic gate that can be designed using a nonhysteretic Josephson weak link is proposed. The basic component of the proposed device is a one-junction interferometer, and a logic state is...