Practical Approximations of Steiner Trees in Uniform Orientation Metrics (2009)
Andrew B. Kahng, Ion Măndoiu, Er Zelikovsky
The Steiner minimum tree problem, which asks for a minimum-length interconnection of a given set of termi-nals in the plane, is one of the fundamental problems in Very Large Scale Integration (VLSI)...
Multicommodity Flow Algorithms for Buffered Global Routing (2008)
Christoph Albrecht, Andrew B. Kahng, Ion Măndoiu, Er Zelikovsky
Due to delay scaling effects in deep-submicron technologies, interconnect planning and synthesis are becoming critical to meeting chip performance targets with reduced design turnaround time. In...
Abstract Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage ∗ (2008)
Puneet Gupta, Andrew B. Kahng, Ion Măndoiu, Puneet Sharma
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay fault testing...
Abstract The Y-Architecture for On-Chip Interconnect: Analysis and Methodology ∗ (2008)
Hongyu Chen, Chung-kuan Cheng, Andrew B. Kahng, Ion Măndoiu, Qinke Wang, Bo Yao
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions exploits on-chip routing...
Yield-driven multi-project reticle design and wafer dicing (2005)
Andrew B. Kahng, Ion Măndoiu, Xu Xu, Alex Z. Zelikovsky
The pervasive use of advanced reticle enhancement technologies demanded by VLSI technology scaling leads to dramatic increases in mask costs. In response to this trend, multiple project wafers (MPW)...
Multi-project reticle floorplanning and wafer dicing (2004)
Andrew B. Kahng, Ion Măndoiu, Qinke Wang, Xu Xu, Alex Z. Zelikovsky
Multi-project Wafers (MPW) are an efficient way to share the rising costs of mask tooling between multiple prototype and low production volume designs. Packing the different die images on a...
The Y-Architecture for on-chip interconnect: Analysis and methodology (2003)
Hongyu Chen, Chung-kuan Cheng, Andrew B. Kahng, Ion Măndoiu, Qinke Wang, Bo Yao
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions exploits on-chip routing...
The Y-Architecture for on-chip interconnect: Analysis and methodology (2003)
Hongyu Chen, Chung-kuan Cheng, Andrew B. Kahng, Ion Măndoiu, Qinke Wang, Bo Yao
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions exploits onchip routing...
Layout-aware scan chain synthesis for improved path delay fault coverage (2003)
Puneet Gupta, Andrew B. Kahng, Ion Măndoiu, Puneet Sharma
Path delay fault testing has become increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay fault testing...
Layout-aware scan chain synthesis for improved path delay fault coverage (2003)
Puneet Gupta, Andrew B. Kahng, Ion Măndoiu, Puneet Sharma
Path delay fault testing has become increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay fault testing...
Floorplan Evaluation with Timing-Driven Global (2002)
Christoph Albrecht, Ý Andrew, B. Kahng, Ion Măndoiu, Er Zelikovsky Þ
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good multi-commodity flow...
Minimum-buffered routing of non-critical nets for slew rate and reliability control (2001)
Charles Alpert, Andrew B. Kahng, Bao Liu, Ion Măndoiu, Er Zelikovsky
In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal transition edges, and...
Selecting forwarding neighbors in wireless ad hoc networks (2001)
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