Janusz Starzyk

Publication List Details

Period

2001 - 2009

Number

7

Co-Authors

Piecewise Linear Approach: a New Approach in Automatic Target Recognition (2009)

Janusz Starzyk

Automatic Target Recognition (ATR) of moving targets has recently received increased interest. High Range Resolution (HRR) radar mode provides a promising approach which relies on processing...

A SELF ORGANIZED CLASSIFIER BASED ON MAXIMUM INFORMATION INDEX AND ITS DEVELOPMENT USING VHDL (2009)

Janusz Starzyk, Yongtao Guo

An entropy-based self organized learning algorithm is presented for classifier design. The method, which is based on ideas from information theory, maximizes the information index during feed forward...

Reconfigurable Self-Organizing NN Design Using Virtex FPGA (2009)

Janusz Starzyk, Yongtao Guo

Abstract In this paper, a self-organizing neural network model with entropy-based evaluator called EBE is proposed. An FPGA based design that implements the EBE model is presented. The PCI bus...

Analog Circuits for Self-Organizing Neural Networks Based on Mutual Information (2009)

Janusz Starzyk, Liang Jing

Abstract – A new self-organizing neural network concept based on mutual information is described in this paper. Comparing to conventional neural network structures, this organization greatly...

Reduct Generation in Information Systems (2008)

Janusz Starzyk, Dale E. Nelson, Kirk Sturtz

Abstract – When data sets are analyzed, statistical pattern recognition is often used to find the information hidden in the data. Another approach to information discovery is data mining. Data...

Software simulation of a self-organizing learning array system (2002)

Janusz Starzyk, Zhen Zhu

A neural network paradigm named Self-Organizing Learning Array system has been simulated in software. Hardware implementation limitations are considered in this simulation. Simulation is performed...

An Entropy-based Learning Hardware Organization Using FPGA (2001)

Janusz Starzyk, Yongtao Guo

Abstract In this paper, a neural network model with entropy-based evaluator called EBE is proposed. An FPGA based design that implements the EBE model is presented. The PCI bus interface including...