Jason D. Bakos

Lightweight Error Correction Coding for System-Level Interconnects (2008)

Jason D. Bakos, Donald M. Chiarulli, Steven P. Levitan, Senior Member

Abstract—“Lightweight Hierarchical Error Control Coding (LHECC) ” is a new class of nonlinear block codes that is designed to increase noise immunity and decrease error rate for...

Lightweight Error Correction Coding for System-Level Interconnects (2008)

Jason D. Bakos, Donald M. Chiarulli, Steven P. Levitan, Senior Member

Abstract—“Lightweight Hierarchical Error Control Coding (LHECC) ” is a new class of nonlinear block codes that is designed to increase noise immunity and decrease error rate for...

Area, Power, and Pin Efficient Bus Transceiver Using Multi-Bit-Differential Signaling (2008)

Donald M. Chiarulli, Jason D. Bakos

Abstract—This paper describes a new low-power, area and pin efficient alternative to differential encoding for high performance chip-to-chip and backplane signaling. The technique, called...

Optoelectronic Multi-Chip Module Demonstrator System (2008)

Jason D. Bakos, Donald Chiarulli, Steven P. Levitan

Abstract: We present our work on a demonstration prototype of an optoelectronic 3-chip OE-

Optoelectronic Multi-Chip Module Demonstrator System (2008)

Jason D. Bakos, Donald M. Chiarulli

Much research has been conducted in the area of optoelectronic interconnection and packaging technology. Much of this work is an effort to develop high bandwidth and low latency optoelectronic...

Efficient Optical Communications Using Multi-Bit Differential Signaling (2008)

Donald M. Chiarulli, Steven P. Levitan, Samuel J. Dickerson, Jason D. Bakos, Joel Martin

We present an alternative signaling method for multi-channel fiber ribbon based optical links. The method is based on a hybrid of differential signaling and single-ended channels. Channels are...

SiGe Prototype Chip Design Implementing CMOS Fixed Bit-Load Drivers and Receivers for Next Generation High-Speed Board-Level Interconnect Abstract Student Designers: (2007)

Jason D. Bakos, Amit Gupta, Leo Salavo, Donald Chiarulli

We present our design and simulation results for a test chip that implements fixed bit-load drivers and receivers. The link architecture that is formed using these circuits offers several...

A reconfigurable distributed computing fabric exploiting multilevel parallelism (2006)

Charles L. Cathey, Jason D. Bakos, Duncan A. Buell

This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This architecture is...

Optoelectronic Multi-Chip-Module Implementation of a 64-Channel Fiber Switch (2002)

Jason D. Bakos, Donald M. Chiarulli, Steven P. Levitan

We present a demonstration prototype of an optoelectronic 3-chip OE-MCM module that implements a 64-channel non-blocking fiber optic switch. Each OE-switch-chip was implemented using Peregrine UTSI...