Interconnection Network and Distributed Shared Memory of a Massively Parallel Machine JUMP-1 (2007)
Hideharu Amano, Katsunobu Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Ken'ichiro Anjo
For cache coherent distributed shared memory on a large scale parallel machine, each node processor of JUMP-1 shares a global virtual address space with two-stage TLB implementation. The directory is...
Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array (2005)
Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura
Abstract. Fat H-Tree is a novel on-chip network topology for a dynamic reconfigurable processor array. It includes both fat tree and torus structure, and suitable to map tasks in a stream processing....
MBP-light: A Processor for Management of Distributed Shared Memory (1998)
Inoue Hiroaki, Katsunobu Nishimura, Mitsuru Satoh, Kei Hiraki, Hideharu Amano
MBP(Memory Based Processor)-light is a dedicated processor for management of cache coherent distributed shared memory (DSM) in a massively parallel processor called JUMP-1. Unlike traditional...
MINC: Multistage Interconnection Network with Cache control mechanism (1997)
Control Mechanism, Toshihiro Hanawa, Takayuki Kamei, Hideki Yasukawa, Katsunobu Nishimura, ...
this paper.
MINC : Multistage Interconnection Network with Cache control mechanism (1996)
Toshihiro Hanawa Hideki, Hideki Yasukawa, Katsunobu Nishimura, Hideharu Amano
A novel approach to the cache coherent Multistage Interconnection Network (MIN) called the MINC (MIN with Cache control mechanism) is proposed. In the MINC, the directory is located only on the...
Tomohiro Kudoh, Hideharu Amano, Takashi Matsumoto, Kei Hiraki, Yulu Yang, Katsunobu Nishimura, ...
JUMP-1 is currently under development by seven Japanese universities to establish techniques of an efficient distributed shared memory on a massively parallel processor. It provides a memory...