Towards the Creation of an ECU Model Exchange Market (2009)
Murakami, Kazuaki, Yoshimatsu, Norifumi, Rao, Pradeep, Oho, Shigeru, Shimada, Satoshi, 村上, 和彰, ...
ICROS-SICE International Joint Conference 2009 : 2009年8月18日(火)～21日(金) : 福岡国際会議場
High-Performance Computation Using a Single-Flux Quantum Accelerator (2009)
Mehdipour, Farhad, Honda, Hiroaki, Kataoka, Hiroshi, Inoue, Koji, Murakami, Kazuaki, 本田, 宏明, ...
The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009) : July 5-8, 2009 : Jeju KAL Hotel, Jeju Island, Korea
Optimizing the architecture of SFQ-RDP (Single Flux Quantum- Reconfigurable Datapath) (2009)
Mehdipour, Farhad, Honda, Hiroaki, Kataoka, Hiroshi, Inoue, Koji, Murakami, Kazuaki, 本田, 宏明, ...
Superconducting SFQ VLSI Workshop (SSV 2009) : 2009年6月15日（月）～17日（水） : The Centennial Hall, Kyushu University School of Medicine, Fukuoka, Japan
Optimizing the Architecture of SFQ-RDP (Single Flux Quantum-Reconfigurable Datapath) (2009)
Mehdipour, Farhad, Honda, Hiroaki, Kataoka, Hiroshi, Inoue, Koji, Murakami, Kazuaki, 本田, 宏明, ...
Superconducting SFQ VLSI Workshop (SSV 2009) in Conjuction with International Superconductive Electronics Conference (ISEC 2009) : June 15-17, 2009 : Kyushu University School of Medicine
Mehdipour, Farhad, Honda, Hiroaki, Kataoka, Hiroshi, Inoue, Koji, Murakami, Kazuaki, 本田, 宏明, ...
Workshop on Accelerators for High-Performance Architecture (WAHA) in Conjunction with 23rd International Conference on Supercomputing (ICS) : June 8-12, 2009 : IBM T.J. Watson Research Center,...
Empirical Performance Models for Java Workloads (2009)
Rao, Pradeep, Murakami, Kazuaki, 村上, 和彰, ムラカミ, カズアキ
The 22nd International Conference on Architecture of Computing Systems (ARCS 2009) : March 10–13, 2009 : Netherlands
A Design Procedure for a Large-Scale Reconfigurable Data-Path (2009)
Honda, Hiroaki, Mehdipour, Farhad, Kataoka, Hiroshi, Inoue, Koji, Murakami, Kazuaki, 本田, 宏明, ...
要求メモリバンド幅を抑えつつも高性能な科学技術計算を可能とするような，大規模再構成可能データパスプロセッサ...
Abstract Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption (2009)
Koji Inoue, Tohru Ishihara, Kazuaki Murakami
This paper proposes a new approach using way prediction for achieving high performance and low energy consumption of set-associative caches. By accessing only a single cache way predicted, instead of...
Mehdipour, Farhad, Noori, Hamid, Javadi, Bahman, Honda, Hiroaki, Inoue, Koji, Murakami, Kazuaki, ...
第14回アジア南太平洋設計自動化会議 (ASP-DAC 2009) : 2009年1月19日(月)～22日(木) : パシフィコ横浜, 横浜市
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints (2008)
Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga
In testing system-on-a-chip (SOC), external pins for test are getting more and more precious hardware resources because the number of external pins is strongly restricted. Cores, which are basic...
LIMITS OF PARALLELISM ON THREAD-LEVEL SPECULATIVE PARALLEL PROCESSING ARCHITECTURE (2008)
Katsuhiko Metsugi, Kazuaki Murakami
Two fundamental restrictions that limit the amount of instructionlevel parallelism extracted from sequential programs are control flow and data flow. TLSP (Thread-Level Speculative Parallel...
The Effect of Temperature on Cache Size Tuning for Low Energy Embedded Systems (2008)
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40 % or more of the total energy consumed in these systems. In...
Using Statistical Models for Embedded Java Performance Analysis (2008)
Rao, Pradeep, Murakami, Kazuaki, 村上, 和彰, ムラカミ, カズアキ
International Conference on High Performance Computing (HiPC 2008) : December 17-20, 2008 : Bangalore, India
Performance Evaluation of a Reconfigurable Instruction Set Processor (2008)
Mehdipour, Farhad, Noori, Hamid, Honda, Hiroaki, Inoue, Koji, Murakami, Kazuaki, 本田, 宏明, ...
International SoC Design Conference (ISOCC 2008) : November 24-25, 2008 : Busan, Korea
Performance Evaluation of a Reconfigurable Instruction Set Processor (2008)
Mehdipour, Farhad, Noori, Hamid, Honda, Hiroaki, Inoue, Koji, Murakami, Kazuaki, 本田, 宏明, ...
International SoC Design Conference (ISOCC 2008) : 2008年11月24日（月）～25日（火） : Busan, Korea
科学技術計算を対象とした大規模再構成可能データパスの性能評価 (2008)
片岡, 広志, 本田, 宏明, Mehdipour, Farhad, 井上, 弘士, 村上, 和彰, Kataoka, Hiroshi, ...
最近，要求メモリバンド幅を抑えつつも高性能な科学技術計算を可能とする，大規模再構成可能データパス（LSRDP）が提案された．本稿ではこのLSRDP...
Noori, Hamid, Mehdipour, Farhad, Inoue, Koji, Murakami, Kazuaki, 井上, 弘士, 村上, 和彰, ...
International Symposium on Low Power Electronics and Design 2008 (ISLPED 2008) : Bangalore, India : August 11-13, 2008
Analyzing the Impact of Data Prefetching on Chip MultiProcessors (2008)
Fukumoto, Naoto, Mihara, Tomonobu, Inoue, Koji, Murakami, Kazuaki, 福本, 尚人, 三原, 智伸, ...
Data prefetching is a well known approach to compensating for poor memory performance, and has been employed in commercial processor chips. Although a number of prefetching techniques have so far...
大規模システム評価環境PSI-SIM : 数千個のマルチコア・プロセッサを搭載したペタスケールコンピュータの性能予測 (2008)
井上, 弘士, 薄田, 竜太郎, 安藤, 壽茂, 石附, 茂, 小松, 秀実, 稲富, 雄一, ...
本稿では，ペタフロップス級スーパーコンピュータの性能予測を可能にするシステム評価環境 PSI-SIM...
演算/メモリ性能バランスを考慮したCMP向けヘルパースレッド実行方式の提案と評価 (2008)
今里, 賢一, 福本, 尚人, 井上, 弘士, 村上, 和彰, Imazato, Kenichi, Fukumoto, Naoto, ...
複数のプロセッサコアを1チップに搭載するチップマルチプロセッサ(CMP)が現在注目されている....
A Sampling Microarchitecture Simulator for Java Workloads (2008)
Rao, Pradeep, Murakami, Kazuaki, 村上, 和彰, ムラカミ, カズアキ
Workshop on Tools, Infrastructures and Methodologies for the Evaluation of Research Systems (TIMERS-1) held in conjunction with the International Symposium on Performance Analysis of Systems and...
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator (2008)
Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami
Abstract. In an embedded system including a base processor integrated with a tightly coupled accelerator, extracting frequently executed portions of the code (hot portion) and executing their...
Reconfigurable Neural Network Using DAP/DNA (2008)
Abstract In this paper, we want to find ways of realizing a neural network in DAP/DNA. As convenient platform for experiments the DAP/DNA were taken, which allows the change of hardware in one clock...
The Effect of Temperature on Cache Size Tuning for Low Energy Embedded Systems (2008)
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40 % or more of the total energy consumed in these systems. In...
REDUCING POWER CONSUMPTION OF INSTRUCTION ROMS BY EXPLOITING INSTRUCTION FREQUENCY (2008)
Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami
This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the switching activity of...
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems (2008)
Sugihara, Makoto, Ishihara, Tohru, Murakami, Kazuaki, 杉原, 真, 石原, 亨, 村上, 和彰, ...
This paper proposes a task scheduling approach for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of...
Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems (2008)
Makoto Sugihara, Tohru Ishihara, Kazuaki Murakami
This paper presents a task scheduling method for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of vulnerable...
森江, 善之, 南里, 豪志, 石畑, 宏明, 井上, 弘士, 村上, 和彰, Morie, Yoshiyuki, ...
本稿では，通信性能の悪化の主要因である通信の衝突を避けるためのタスク配置最適化の評価を行った．著者らはメッセージのタイミングを制御し...
A Hybrid Design Space Exploration Approach for a Coarse-Grained Reconfigurable Accelerator (2008)
Mehdipour, Farhad, Noori, Hamid, Honda, Hiroaki, Inoue, Koji, Murakami, Kazuaki, 本田, 宏明, ...
第133回 システムLSI設計技術研究発表会 : 2008-01-16～2008-01-17 : 神奈川
演算/メモリ性能バランスを考慮したCMP向けオンチップ・メモリ貸与法の提案 (2008)
林, 徹生, 今里, 賢一, 井上, 弘士, 村上, 和彰, Hayashi, Tetsuo, Imazato, Kenichi, ...
第168回 計算機アーキテクチャ・第7回 組込みシステム 合同研究発表会 : 2008年1月15日(火)～2008年1月16日(水) : 神奈川
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems (2008)
SUGIHARA, Makoto, ISHIHARA, Tohru, MURAKAMI, Kazuaki
This paper proposes a task scheduling approach for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of...
Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems (2008)
NOORI, Hamid, GOUDARZI, Maziar, INOUE, Koji, MURAKAMI, Kazuaki
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for 40% or more of the total energy consumed in these systems....
NOORI, Hamid, MEHDIPOUR, Farhad, INOUE, Koji, MURAKAMI, Kazuaki
Encapsulating critical computation subgraphs as applica-tion-specific instruction set extensions is an effective technique to enhance the performance of embedded processors. However, the addition of...
TAKAGI, Naofumi, MURAKAMI, Kazuaki, FUJIMAKI, Akira, YOSHIKAWA, Nobuyuki, INOUE, Koji, HONDA, Hiroaki
We propose a desk-side supercomputer with large-scale reconfigurable data-paths (LSRDPs) using superconducting rapid single-flux-quantum (RSFQ) circuits. It has several sets of computing unit which...
Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems (2008)
SUGIHARA, Makoto, MATSUNAGA, Yusuke, MURAKAMI, Kazuaki
Character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask manufacture because it can project ICs much faster than point beam projection or...
Performance Models for MPI Collective Communications with Network Contention (2008)
NZIGOU MAMADOU, Hyacinthe, NANRI, Takeshi, MURAKAMI, Kazuaki
The paper presents a novel approach to estimate the performance of MPI collective communications. Our objective is to help researchers to make appropriate decisions on their message-passing...
Energy Consumption Evaluation of an Adaptive Extensible Processor (2007)
Noori, Hamid, Mehdipour, Farhad, Goudarzi, Maziar, Yamaguchi, Seiichiro, Inoue, Koji, Murakami, Kazuaki, ...
Second Annual Reconfigurable and Adaptive Architecture Workshop (RAAW-2) : Dec. 1, 2007 : Chicago,Illinois, USA
Mehdipour, Farhad, Noori, Hamid, Zamani, Morteza Saheb, Inoue, Koji, Murakami, Kazuaki, 井上, 弘士, ...
Extracting frequently executed (hot) portions of the application and executing their corresponding data flow graph (DFG) on the hardware accelerator brings about more speedup and energy saving for...
Koji Inoue, Koji Kai, Kazuaki Murakami
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache (D-VLS cache)". The D-VLS cache can...
Parallel Processing RAM (PPRAM) (2007)
Kazuaki Murakami, Koji Inoue, Hiroshi Miyajima
framework for merged memory/logic ASSPs(Application-Specific Standard Products). At first, the paper discusses the serious problems that the current high-performance microprocessor-based systems are...
Bitslice-Datapath Architecture for Multimedia Processing and Power-Consumption Reduction (2007)
Satoru Shirakawa, Koji Inoue, Kazuaki Murakami
This paper proposes a new processor architecture, called "bitslice-datapath architecture, " and discusses its effectiveness. The datapath (registers and functional units) of...
A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips (2007)
SAKAMOTO, Mariko, KATSUNO, Akira, SUGIZAKI, Go, YOSHIDA, Toshio, INOUE, Aiichiro, INOUE, Koji, ...
Broadcast and synchronization techniques are used for cache coherence control in conventional larger scale snoop-based SMP systems. The penalty for synchronization is directly proportional to system...
Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems (2007)
SUGIHARA, Makoto, ISHIHARA, Tohru, MURAKAMI, Kazuaki
This paper proposes a soft-error model for accurately estimating reliability of a computer system at the architectural level within reasonable computation time. The architectural-level soft-error...
High Performance, Low Power Reconfigurable Processor for Embedded Systems (2007)
Mehdipour, Farhad, Noori, Hamid, Inoue, Koji, Murakami, Kazuaki, 井上, 弘士, 村上, 和彰, ...
International SoC Design Conference : October 15-16 : Korea
森江, 善之, 末安, 直樹, 松本, 透, 南里, 豪志, 石畑, 宏明, 井上, 弘士, ...
本稿では，通信の衝突を回避するためのタスク配置最適化の提案を行う．提案手法は通信パターンを抽出したプログラムを用いた性能評価実験にお...
Implementation and Evaluation of Fock Matrix Calculation Program on the Cell Processor (2007)
Honda, Hiroaki, Hayashi, Tetsuo, Inadomi, Yuichi, Inoue, Koji, Murakami, Kazuaki, 本田, 宏明, ...
ICCMSE 2007 : 25-30 September 2007 : Greece
メモリアクセスの特徴を活用した高速かつ正確なメモリアーキテクチャ・シミュレーション法 (2007)
小野, 貴継, 井上, 弘士, 村上, 和彰, Ono, Takatsugu, Inoue, Koji, Murakami, Kazuaki, ...
本稿では,高速かつ正確なメモリアーキテクテャ・シミュレーション法を提案する.一般に,メモリアーキテクチャの評価には,メモリ参照のアドレス・...
通信タイミングを考慮した衝突削減のためのMPIランク配置最適化技術 (2007)
森江, 善之, 末安, 直樹, 松本, 透, 南里, 豪志, 石畑, 宏明, 井上, 弘士, ...
本稿では,通信性能の悪化の主要因である通信の衝突を避けるためのランク配置最適化技術の提案を行う.通信のタイミングを考慮することで,通信の...
大規模並列システムの性能評価を目的としたプログラムコード抽象化技法 (2007)
松本, 幸, 本田, 宏明, 稲富, 雄一, 薄田, 竜太郎, 柴村, 英智, 井上, 弘士, ...
2007-HPC-111
Noori, Hamid, Goudarzi, Maziar, Inoue, Koji, Murakami, Kazuaki, 井上, 弘士, 村上, 和彰, ...
Several studies have shown that cache memories account for more than 40% of the total energy consumed in processor-based embedded systems. In microscale technology nodes, active power is the primary...
大規模再構成可能データパスにおけるオンチップ・ネットワーク・アーキテクチャの検討 (2007)
島崎, 慶太, 長野, 孝昭, 本田, 宏明, メディプー, ファラハド, 井上, 弘士, 村上, 和彰, ...
2007-ARC-173
高速かつ正確なキャッシュシミュレーション法とその評価 (2007)
小野, 貴継, 井上, 弘士, 村上, 和彰, Ono, Takatsugu, Inoue, Koji, Murakami, Kazuaki, ...
2007-ARC-173
通信タイミングを考慮した衝突削減のためのMPIランク配置最適化技術 (2007)
森江, 善之, 末安, 直樹, 松本, 透, 南里, 豪志, 石畑, 宏明, 井上, 弘士, ...
第5回先進的計算基盤システムシンポジウム, SACSIS 2007 (5th Symposium on Advanced Computing Systems and Infrastructures) : 学術総合センター講堂・会議室(東京) :...
メモリアクセスの特徴を活用した高速かつ正確なメモリアーキテクチャ・シミュレーション法 (2007)
小野, 貴継, 井上, 弘士, 村上, 和彰, Ono, Takatsugu, Inoue, Koji, Murakami, Kazuaki, ...
第5回先進的計算基盤システムシンポジウム SACSIS 2007 : 5th Symposium on Advanced Computing Systems and Infrastructures : 2007年5月23日(水)～25日(金) :...
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator (2007)
Noori, Hamid, Mehdipour, Farhad, Zamani, Morteza Saheb, Inoue, Koji, Murakami, Kazuaki, 井上, 弘士, ...
the 3rd International Conference on Embedded Software and Systems, ICESS 2007 : 14-16 May, 2007 : Korea : The proceedings are published by Springer 's Lecture Notes in Computer Science (LNCS).
Technology Mapping Technique for Increasing Throughput of Character Projection Lithography (2007)
SUGIHARA, Makoto, NAKAMURA, Kenta, MATSUNAGA, Yusuke, MURAKAMI, Kazuaki
The character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask fabrication. The drawback of the CP lithography is its low throughput and...
動的再構成可能プロセッサVulcan2 とそのソフトウェア開発環境ISAcc に関する研究 (2007)
平木, 哲夫, 門内, 伸吾, 山崎, 陽介, 神戸, 隆行, Gauthier, Lovic, Mauro Goulart Ferreira, Victor, ...
特定用途向けプロセッサとは，アプリケーションに特化した命令を実行することによって，汎用プロセッサに対して高性能を実現するものである．...
チップマルチプロセッサにおけるデータ・プリフェッチ効果の分析 (2007)
福本, 尚人, 三原, 智伸, 井上, 弘士, 村上, 和彰, Fukumoto, Naoto, Mihara, Tomonobu, ...
複数コアを１チップに搭載するチップマルチプロセッサ(CMP)が注目されている。CMP...
The Potential of Temperature-Aware Configurable Cache on Energy Reduction (2007)
Noori, Hamid, Goudarzi, Maziar, Inoue, Koji, Murakami, Kazuaki, 井上, 弘士, 村上, 和彰, ...
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of digital systems...
Dynamic Management Technique to Mitigate Performance Degradation for Low-Leakage Caches (2007)
Komiya, Reiko, Inoue, Koji, Murakami, Kazuaki, 小宮, 礼子, 井上, 弘士, 村上, 和彰, ...
Cool Chips X : the 10th anniversary of IEEE Symposium on Low-Power and High-Speed Chips : April 18-20, 2007 : Yokohama, Japan
Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor (2007)
Noori, Hamid, Mehdipour, Farhad, Murakami, Kazuaki, Inoue, Koji, Goudarzi, Maziar, 村上, 和彰, ...
To improve the performance of embedded processors, an effective technique is collapsing critical computation subgraphs as application-specific instruction set extensions and executing them on custom...
The Effect of Temperature on Cache Size Tuning for Low Energy Embedded Systems (2007)
Noori, Hamid, Goudarzi, Maziar, Inoue, Koji, Murakami, Kazuaki, 井上, 弘士, 村上, 和彰, ...
The 17th edition of ACM Great Lakes Symposium on VLSI (GLSVLSI) : March 11-13, 2007 : Stresa-Lago Maggiore, Italy
森江, 善之, 末安, 直樹, 松本, 透, 南里, 豪志, 石畑, 宏明, 井上, 弘士, ...
本稿では，通信性能の悪化の主要因である通信の衝突を避けるためのランク配置最適化技術の提案を行う．メッセージごとに通信のタイミングを考...
Bit-parallel Computation for Wavefront Algorithm (2007)
E, Hanmei, Baba, Kensuke, Yu, Yunqing, Murakami, Kazuaki, 鄂, 寒梅, 馬場, 謙介, ...
This paper presents a parallel algorithm for solving the edit distance problem. The edit distance represents a similarity of two strings and the dynamic programming approach is a general paradigm to...
Custom Instructions with Multiple Exits: Generation and Execution (2007)
Noori, Hamid, Mehdipour, Farhad, Inoue, Koji, Murakami, Kazuaki, Goudarzi, Maziar, 井上, 弘士, ...
In this paper, we propose an adaptive extensible processor in which custom instructions are generated and added after chip-fabrication. A reconfigurable functional unit is utilized to support this...
MEHDIPOUR, Farhad, NOORI, Hamid, SAHEB ZAMANI, Morteza, INOUE, Koji, MURAKAMI, Kazuaki
Extracting frequently executed (hot) portions of the application and executing their corresponding data flow graph (DFG) on the hardware accelerator brings about more speedup and energy saving for...
Approximate String Matching Based on Bit Operations (2006)
E, Hanmei, Yu, Yunqing, Baba, Kensuke, Murakami, Kazuaki, 鄂, 寒梅, 于, 雲青, ...
International Conference of Computational Methods in Sciences and Engineering 2006 (ICCMSE 2006)
Bit-parallel Computation for String Alignment (2006)
Yu, Yunqing, Baba, Kensuke, E, Hanmei, Murakami, Kazuaki, 于, 雲青, 馬場, 謙介, ...
International Conference of Computational Methods in Sciences and Engineering 2006 (ICCMSE 2006)
Mehdipour, Farhad, Noori, Hamid, Saheb Zamani, Morteza, Murakami, Kazuaki, Sedighi, Mehdi, Inoue, Koji, ...
Extensible processors allow customization for an application by extending the core instruction set architecture. Extracting appropriate custom instructions is an important phase for implementing an...
Mehdipour, Farhad, Noori, Hamid, Saheb Zamani, Morteza, Murakami, Kazuaki, Inoue, Koji, Sedighi, Mehdi, ...
Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit (RFU). Custom instructions (CIs) are...
A RECONFIGURABLE FUNCTIONAL UNIT FOR AN ADAPTIVE DYNAMIC EXTENSIBLE PROCESSOR (2006)
Noori, Hamid, Mehdipour, Farhad, Murakami, Kazuaki, Inoue, Koji, SahebZamani, Morteza, 村上, 和彰, ...
This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after...
REDEFIS : A System with a Redefinable Instruction Set Processor (2006)
Goulart Ferreira, Victor M., Gauthier, Lovic, Kando, Takayuki, Matsuo, Takuma, Hashinaga, Toshihiko, Murakami, Kazuaki, ...
The 19th Annual Symposium on Integrated Circuits and Systems Design : Brazil : August 28 - September 1, 2006
演算結果再利用による高信頼かつ低消費電力なプロセッサに関する検討 (2006)
橋口, 陽祐, 井上, 弘士, 村上, 和彰, Hashiguchi, Yosuke, Inoue, Koji, Murakami, Kazuaki, ...
情報処理学会計算機アーキテクチャ研究会 : 2006年6月8-9日 : NEC玉川ルネッサンスシティ, 神奈川
A Reconfigurable Functional Unit for Adaptable Custom Instructions (2006)
Noori, Hamid, Mehdipour, Farhad, Murakami, Kazuaki, Inoue, Koji, SahebZamani, Morteza, 村上, 和彰, ...
This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target applications, after...
Mehdipour, Farhad, Saheb Zamania, Morteza, Sedighi, Mehdi, Murakami, Kazuaki, Noori, Hamid, 村上, 和彰, ...
In reconfigurable systems, reconfiguration latency has a significant impact on the system performance. In this work, a temporal partitioning algorithm is presented to partition data flow graphs for...
待機ラインへの参照密度に基づく低リーク･キャッシュの高性能化 (2006)
小宮, 礼子, 井上, 弘士, 村上, 和彰, Komiya, Reiko, Inoue, Koji, Murakami, Kazuaki, ...
Symposium on Advanced Computing Systems and Infrastructures 2006 (SACSIS 2006) : May 22-24, 2006 : Osaka, JAPAN
Noori, Hamid, Murakami, Kazuaki, 村上, 和彰, ノーリ, ハミッド
In this research we investigate an approach for adaptive dynamic instruction set extension, tuning processors to specific applications after fabrication.
Performance Optimization for Low-Leakage Caches based on Sleep-Line Access Density (2006)
Komiya, Reiko, Inoue, Koji, Murakami, Kazuaki, 小宮, 礼子, 井上, 弘士, 村上, 和彰, ...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, NY
An Online Profiling-Based Dynamically Adaptable Processor (2006)
Noori, Hamid, Yoshimatsu, Norifumi, Fujii, Yousuke, Eshima, Kazuhito, Yoshida, Makoto, Soga, Takeshi, ...
This paper investigates a possible architecture to a dynamically adaptable processor. In this architecture, the running application is profiled and dynamic traces of high frequently executed loops...
橋永, 寿彦, Gauthier, Lovic, 神戸, 隆行, Ferreira, Victor Mauro Goulart, 薄田, 竜太郎, 平木, 哲夫, ...
特定用途向けプロセッサとは，アプリケーションに特化した命令を実行することによって，汎用プロセッ...
Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue†† Mehdi
Abstract. Extracting appropriate custom instructions is an important phase for implementing an application on an extensible processor with a reconfigurable functional unit (RFU). Custom instructions...
SUGIHARA, Makoto, TAKATA, Taiga, NAKAMURA, Kenta, INANAMI, Ryoichi, HAYASHI, Hiroaki, KISHIMOTO, Katsumi, ...
We propose a cell library development methodology for throughput enhancement of character projection equipment. First, an ILP (Integer Linear Programming)-based cell selection is proposed for the...
常活性ラインに基づく高性能/低リーク・キャッシュの消費エネルギー評価 (2005)
小宮, 礼子, 井上, 弘士, 村上, 和彰, Komiya, Reiko, Inoue, Koji, Murakami, Kazuaki, ...
我々はこれまでに,...
An Adaptive Dynamic Extensible Processor (2005)
Noori, Hamid, Murakami, Kazuaki, Inoue, Koji, 村上, 和彰, 井上, 弘士, ノーリ, ハミッド, ...
デザインガイア2005 : 2005年11月30日(水)－12月2日(金) : 北九州国際会議場
An Adaptive Dynamic Extensible Processor (2005)
Noori, Hamid, Murakami, Kazuaki, Inoue, Koji, 村上, 和彰, 井上, 弘士, ノーリ, ハミッド
This paper describes an approach for adaptive dynamic instruction set extension, tuning processors to specific applications. These new instructions are generated after production. The processor has...
三輪, 英樹, 堂後, 靖博, 井上, 弘士, 村上, 和彰, Miwa, Hideki, Dougo, Yasuhiro, ...
近年，マイクロプロセッサの性能は半導体製造技術の進歩に伴い飛躍的に向上した．一方，主記憶 として利用されるDRAM...
待機ラインへの参照密度に基づく低リーク・キャッシュの動的制御 (2005)
小宮, 礼子, 井上, 弘士, 村上, 和彰, Komiya, Reiko, Inoue, Koji, Murakami, Kazuaki, ...
これまでに多くの低リーク・キャッシュが提案された．しかしながら，これらの手法は待機状態ラインのデータを破棄するため，ミス回数が増加し...
キャッシュ・ミス頻発ロード命令を対象としたミス原因解析 (2005)
三輪, 英樹, 堂後, 靖博, 井上, 弘士, 村上, 和彰, Miwa, Hideki, Dougo, Hiroyasu, ...
近年，マイクロプロセッサの性能は半導体製造技術の進歩に伴い飛躍的に向上した．その一方で，主記憶 として利用されるDRAM...
大学でシステムLSI（アーキテクチャ）をどう教育するか？ (2005)
村上, 和彰, Murakami, Kazuaki, ムラカミ, カズアキ
システムLSI国際シンポジウム : 北九州学術研究都市会議場, 北九州
Redefis : An SoCPlatform for Implementing Application-Specific or User-Custom Logic (2005)
Murakami, Kazuaki, 村上, 和彰, ムラカミ, カズアキ
MPSoC 2005 International Seminar on Application-Specific : Margaux, France
「標準/汎用SoCプラットフォーム」を目指すダイナミックリコンフィギュラブルプロセッサの最新動向 (2005)
村上, 和彰, Murakami, Kazuaki, ムラカミ, カズアキ
第8回組込みシステム開発技術展 : 2005.6.29 : 東京ビッグサイト
SysteMorph: AnSoC Framework for Adaptive Dynamic Optimization Systems (2005)
Noori, Hamid, Eshima, Kazuhito, Fujii, Yousuke, Yoshida, Makoto, Soga, Takeshi, Yoshimatsu, Norifumi, ...
The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'05), Jul. 2005.
Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches (2005)
Komiya, Reiko, Inoue, Koji, Moshnyaga, Vasily G., Murakami, Kazuaki, 小宮, 礼子, 井上, 弘士, ...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become an inevitable issue for high-performance microprocessor designs. Since on-chip caches are major...
将来（2010年前後を想定）のペタフロップス超級スパコンセンターとの連携について (2005)
村上, 和彰, Murakami, Kazuaki, ムラカミ, カズアキ
文部科学省計算科学技術推進ワーキンググループ会議
Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches (2005)
KOMIYA, Reiko, INOUE, Koji, MOSHNYAGA, Vasily G., MURAKAMI, Kazuaki
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become an inevitable issue for highperformance microprocessor designs. Since on-chip caches are major...
待機状態ラインに対する参照局所性を考慮した低リーク・キャッシュの性能低下抑制方式 (2004)
小宮, 礼子, 井上, 弘士, モシニャガ, ワシリー, 村上, 和彰, Komiya, Reiko, Inoue, Koji, ...
これまでに多くの低リーク・キャッシュが提案されてきた．しかしながら，これらの手法を用いると...
キャッシュ・ミス頻発命令を考慮したメモリ・システムの高性能化 (2004)
三輪, 英樹, 堂後, 靖博, グラール フェヘイラ, ヴィクトル マウロ, 井上, 弘士, 村上, 和彰, Miwa, Hideki, ...
マイクロプロセッサと主記憶との動作周波数差は，年々拡大する一方である．両者の周波数差は，マ...
堂後, 靖博, 三輪, 英樹, グラール フェヘイラ, ヴィクトル マウロ, 井上, 弘士, 村上, 和彰, Dougo, Yasuhiro, ...
メモリ・ウォール問題（プロセッサ－主記憶間の性能差拡大）を解決する有効な手段の1 つとして， Delinquent 命令の活用がある．例えば，Delinquent...
動的システム最適化技術SysteMorphの予備性能評価 (2004)
江島, 和仁, 吉松, 則文, 曽我, 武史, 村上, 和彰, Eshima, Kazuhito, Yoshimatsu, Norifumi, ...
コンピュータのハードウェアや，ソフトウェアを動的に最適化する「動的システム最適化技術」が注目さ れている．筆者らはSysteMorph...
Vulcan ～Redefisの一実施例とそれへのユーザ機能実装例の紹介～ (2004)
橋永, 寿彦, 首藤, 真, 松尾, 拓真, 森江, 善之, Gauthier, Lovic, 村上, 和彰, ...
ユーザ機能の実装に適したSoC プラットフォームRedefis の一実施例である，プロセッサVulcan について 紹介し，さらにVulcan...
A Low Power I-Cache Design with Tag-Comparison Reuse (2004)
Inoue, Koji, Tanaka, Hidekazu, Moshnyaga, Vasily G., Murakami, Kazuaki, 井上, 弘士, 田中, 秀和, ...
This paper reports design and evaluation results of a low-energy I-cache architecture, called history-based tagcomparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results to...
Just-in-Time HW/ISA/SW Co-optimization Techniques for SoC (2004)
Murakami, Kazuaki, Mauro Goulart Ferreira, Victor, 村上, 和彰, ムラカミ, カズアキ
SBAC-PAD2004 Tutorial Foz do Iguacu
Quantitative Evaluation of Leakage Reduction Algorithm for L1 Data Caches (2004)
Komiya, Reiko, Inoue, Koji, Moshnyaga, Vasily G., Murakami, Kazuaki, 小宮, 礼子, 井上, 弘士, ...
A number of techniques to reduce cache leakage have so far been proposed. However, it is not clear that 1) what kind of algorithm can be considered and 2) how much they have impact on energy and...
マルチ・スレッド実行を前提としたキャッシュ・リーク削減アルゴリズムの評価 (2004)
小宮, 礼子, 井上, 弘士, モシニャガ, ワシリー, 村上, 和彰, Komiya, Reiko, Inoue, Koji, ...
SysteMorph Prototyping on DAP/DNA (2004)
Yoshida, Makoto, Soga, Takeshi, Yoshimatsu, Norifumi, Murakami, Kazuaki, 吉田, 真, 曽我, 武史, ...
Dynamic optimization for software and hardware is gaining attention of computer system researchers. We are researching Systemorph technology. SysteMorph is a dynamic optimization technology proposed...
SysteMorph: Dynamic/Online/Adaptive System-Level Optimization for SoC (2004)
Yoshimatsu, Norifumi, Yoshida, Makoto, Soga, Takeshi, Shuto, Makoto, Tanoue, Yasuyuki, Fujii, Yosuke, ...
This paper describes SysteMorph, a feedback directed dynamic, online and adaptive hardware/instruction set architecture (ISA)/software co-optimization technology. The technology enables to optimize...
Reconfigurable Neural Network Using DAP/DNA (2004)
Yu, Yunqing, Murakami, Kazuaki, 于, 雲青, 村上, 和彰, ウ, ウンセイ
In this paper, we want to find ways of realizing a neural network in DAP/DNA. As convenient platform for experiments the DAP/DNA were taken, which allows the change of hardware in one clock per...
マッスル・サーバー（汎用PCクラスタ＋特定計算向けハードウェア）の開発 : 分子軌道法を例にして (2004)
村上, 和彰, Murakami, Kazuaki, ムラカミ, カズアキ
筑波大学計算科学研究センター発足シンポジウム「計算科学による新たな知の発見・統合・創出」 : 2004.6.10-11 : 筑波大学大学会館国際会議室
キャッシュ・リーク電力削減アルゴリズムに関する定量的評価 (2004)
小宮, 礼子, 井上, 弘士, モシニャガ, ワシリー, 村上, 和彰, Komiya, Reiko, Inoue, Koji, ...
第17回 回路とシステム軽井沢ワークショップ (The 17th Workshop on Circuits and Systems in Karuizawa) : 軽井沢プリンスホテル : 2004年4月26日(月)-27日(火)
Test architecture exploration on reconfigurable scan chain network (2004)
Sugihara, Makoto, Murakami, Kazuaki, 杉原, 真, 村上, 和彰
In this paper, a test architecture exploration on reconfigurable scan chain network is discussed. Reconfigurable scan chain network enables system integrators to optimize their test designs without...
ヒストリ・ベース・タグ比較キャッシュの設計と評価 (2004)
田中, 秀和, 井上, 弘士, モシニャガ, ワシリー, 村上, 和彰, Tanaka, Hidekazu, Inoue, Koji, ...
Practical test architecture optimization for system-on-a-chip under floorplanning constraints (2004)
Sugihara, Makoto, Murakami, Kazuaki, Matsunaga, Yusuke, 杉原, 真, 村上, 和彰, 松永, 裕介
In testing system-on-a-chip (SOC), external pins for test are getting more and more precious hardware resources because the number of external pins is strongly restricted. Cores, which are basic...
DAP/DNAを用いたSysteMorphプロトタイピング (2003)
吉田, 真, 曽我, 武史, 村上, 和彰, 林田, 隆則, Yoshida, Makoto, Soga, Takeshi, ...
近年，再構成可能なシステムを用いた動的最適化技術に注目が集まっている. 我々は, 九州大学にて 研究されているSysteMoprh...
Hayashida, Takanori, Murakami, Kazuaki, 林田, 隆則, 村上, 和彰
Online profiling methodologies are studied for exploiting dynamic optimization. On a dynamic optimizable system with online profilers, it has to get accurate profile in early step of the program...
Dynamic Effective Precision Matching Computation (2003)
Goulart, Victor, Murakami, Kazuaki, 村上, 和彰, グラール, ヴィクトル
In this paper, the authors discuss fine-grain power savings obtained through a technique which we call Effective Precision Matching Computation—PreMatch. It works by dynamically selecting...
Eric(二電子積分計算専用プロセッサ)LSIの開発 (2003)
原田, 宗幸, 中村, 健太, 桑山, 庸史, 上原, 正光, 佐藤, 比佐夫, 小原, 繁, ...
筆者らは,非経験的分子軌道計算を高速に処理する専用並列計算機システムに搭載する,二電子積分計算専用プロセッサ,Ericの開発を行っている.二電子...
Eric: A Special-Purpose Processor for ERI Calculations in Quantum Chemistry Applications (2002)
Nakamura, Kenta, Hatae, Hidenori, Harada, Muneyuki, Kuwayama, Yoji, Uehara, Masamitsu, Sato, Hisao, ...
HPC-Asia 2002, Dec. 2002.
スレッドレベル投機的並列処理アーキテクチャにおけるデータ依存制約緩和手法の効果 (2002)
目次, 勝彦, 村上, 和彰, Metsugi, Katsuhiko, Murakami, Kazuaki
プログラムを並列実行する際に並列度を決定する要因となるのは, 主に命令間のデータ依存と制御依 存である．本論文では3...
A front - end for better behavioral synthesis (2002)
Gauthier, Lovic, Devroye, Natasha, Tomiyama, Hiroyuki, Murakami, Kazuaki, 冨山, 宏之, 村上, 和彰, ...
By allowing higher-level descriptions, behavioral synthesis helps to cope with the growing chips' complexity. However, its efficiency has never met the one of RTL synthesis. Our goal is to define a...
Reducing Power Consumption of Instruction ROMs by Exploiting Instruction Frequency (2002)
Inoue, Koji, Moshnyaga, Vasily G., Murakami, Kazuaki, 井上, 弘士, 村上, 和彰, モシニャガ, ワシリー
Proc. of 2002 IEEE ASIA Pacific Conference on Circuits And Systems (APCCAS'02), Oct. 2002.
スレッドレベル投機的並列処理アーキテクチャにおけるデータ依存制約緩和手法の効果 (2002)
目次, 勝彦, 村上, 和彰, Metsugi, Katsuhiko, Murakami, Kazuaki
プログラムを並列実行する際に並列度を決定する要因となるのは, 主に命令間のデータ依存と制御依 存である．本論文では3...
A Low Energy Set-Associative I-Cashe with Extended BTB (2002)
Inoue, Koji, Moshnyaga, Vasily G., Murakami, Kazuaki, 井上, 弘士, 村上, 和彰, モニシャガ, ワシリー
This paper proposes a low-energy instruction-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results for avoiding unnecessary...
A History-Based I-Cashe for Low-Energy Multimedia Applications (2002)
Inoue, Koji, Moshnyaga, Vasily G., Murakami, Kazuaki, 井上, 弘士, 村上, 和彰, モシニャガ, ワシリー
This paper proposes a history-based tag-comparison scheme for reducing energy consumption of direct-mapped instruction caches. The proposed cache efficiently exploits programexecution footprints...
動的ソフトウェアパイプライニング技術の提案と性能評価 (2002)
田上, 裕之, 村上, 和彰, Tanoue, Yasuyuki, Murakami, Kazuaki
コンピュータのハードウェアやソフトウェアを動的に最適化する「動的最適化技術」が注目されている．筆者らは，動的最適化技術の1つである動的...
Dependable Pipelining マルチGHz時代のマイクロアーキテクチャ (2002)
松尾, 烈, 藤川, 卓也, 目次, 勝彦, 村上, 和彰, Matsuo, Tsuyoshi, Fujikawa, Takuya, ...
微細加工技術の進歩に伴い,回路遅延における配線遅延の支配化問題が浮上してきている.そこで,本稿では配線遅延の支配化問題を考慮した次世代マ...
SYSTEMORPH: Functionality Morphing (2002)
林田, 隆則, 數, 勇介, 村上, 和彰, Hayashida, Takanori, Kazu, Yuusuke, Murakami, Kazuaki
SWEST4
Limits of Parallelism on Thread-Level Speculative Parallel Processing Architecture (2002)
Metsugi, Katsuhiko, Murakami, Kazuaki, 目次, 勝彦, 村上, 和彰
International Workshop on Informationons and Electrical Engineering (IWIE2002)
低消費電力メディア・アプリケーション向けヒストリ・ベース・タグ比較キャッシュの評価 (2002)
井上, 弘士, Moshnyaga, Vasily G., 村上, 和彰, Inoue, Koji, Moshnyaga, Vasily G., Murakami, Kazuaki, ...
これまでに我々は，ダイレクト・マップ命令キャッシュの低消費エネルギー化を目的として，ヒストリ・ ベース・タグ比較(HBTC: History Based...
実行頻度の偏りを利用した命令コード割り当てによる命令ROMの低消費電力化 (2002)
井上, 弘士, モシニャガ, ワシリー, 村上, 和彰, Inoue, Koji, Moshnyaga, Vasily G., Murakami, Kazuaki, ...
タグ比較結果の再利用に基づくメディア・アプリケーション向け低消費電力キャッシュ (2002)
井上, 弘士, Moshnyaga, Vasily G., 村上, 和彰, Inoue, Koji, Murakami, Kazuaki, モニシャガ, ワシリー
中村, 健太, 波多江, 秀典, 原田, 宗幸, 上原, 正光, 佐藤, 比佐夫, 小原, 繁, ...
筆者らは，非経験的分子軌道計算を高速に処理することを目的とする，二電子積分計算専用プロセッサの開発を行っている．二電子積分計算のアル...
Trends in High-Performance, Low-Power Cache Memory Architectures (2002)
Inoue, Koji, Moshnyaga, Vasily G., Murakami, Kazuaki, 井上, 弘士, 村上, 和彰, モニシャガー, ワシリー
One of uncompromising requirements from portable computing is energy efficiency, because that affects directly the battery life. On the other hand, portable computing will target more demanding...
Inoue, Koji, Moshnyaga, Vasily G., Murakami, Kazuaki, 井上, 弘士, 村上, 和彰, モシニャガ, ワシリー
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-based tag-comparison (HBTC) cache”. The HBTC cache attempts to detect and omit unnecessary tag...
指数関数演算回路における性能／面積間のトレードオフに関する評価 (2002)
波多江, 秀典, 橋本, 浩二, 村上, 和彰, Hatae, Hidenori, Hashimoto, Koji, Murakami, Kazuaki
トランジスタ集積度の飛躍的な向上に伴い，LSI に搭載される算術演算回路の規模，複雑度が増加している．すな...
Koji Inoue, Vasily Moshnyaga, Kazuaki Murakami
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-based tag-comparison (HBTC) cache”. The HBTC cache attempts to detect and omit unnecessary tag...
Trends in High-Performance, Low-Power Cache Memory Architectures (2002)
Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami
One of uncompromising requirements from portable computing is energy efficiency, because that affects directly the battery life. On the other hand, portable computing will target more demanding...
タグ比較結果の再利用によるキャッシュメモリの低消費電力化 (2001)
井上, 弘士, Moshnyaga G., Vasily, 村上, 和彰, Inoue, Koji, Moshnyaga G., Vasily, Murakami, Kazuaki, ...
本稿では，低消費エネルギー化を実現する新しい命令キャッシュ・アーキテクチャとして、ヒストリ・ベース・ルックアップ・キャッシュ（HBLキャ...
Modeling Fixed-Priority Preemptive Multi-Task Systems in SpecC (2001)
Tomiyama, Hiroyuki, Cao, Yun, Murakami, Kazuaki, 冨山, 宏之, 曹, ユン, 村上, 和彰, ...
Many real-world embedded systems employ a preemptive scheduling policy in order to satisfy their real-time requirements. However, most System-Level Design Languages (SLDLs) which were proposed up to...
DRAM/ロジック混載LSI向け高性能/低消費電力キャッシュ・アーキテクチャ (2001)
井上, 弘士, 石原, 亨, 甲斐, 康司, 村上, 和彰, Inoue, Koji, Ishihara, Tohru, ...
DRAMとロジックの混載は,...
A Low-Power Instruction Cache Architecture Exploiting Program Execution Footprints (2001)
Inoue, Koji, Murakami, Kazuaki, 井上, 弘士, 村上, 和彰, イノウエ, コウジ, ムラカミ, カズアキ
Seventh International Symposium on High Performance Computer Architecture (HPCA-7), Work in Progress Session : January 20-24, 2001 : Monterrey, Mexico
Development of PPRAM-Link Interface (PLIF) IP Core for High-Speed Inter-SoC Communication (2001)
Okuma, Takanori, Hashimoto, Koji, Murakami, Kazuaki, 大隈, 孝憲, 村上, 和彰, オオクマ, タカノリ, ...
Asia South Pacific Design Automation Conference 2001 (ASP-DAC 2001) : 2001年1月30日(火) - 2月2日(金) : パシフィコ横浜
Modeling fixed-priority preemptive multi-task systems in SpecC (2001)
Hiroyuki Tomiyama, Yun Cao, Kazuaki Murakami
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Omitting Cache Look-Up for High-Performance, Low-Power Microprocessors (2001)
Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami
SUMMARY In this paper, we propose a novel architecture for low-power direct-mapped instruction caches, called “historybased tag-comparison (HBTC) cache”. The cache attempts to reuse...
実行履歴に基づいた低電力命令キャッシュ向けタグ比較回数削減手法 (2000)
井上, 弘士, 村上, 和彰, Inoue, Koji, Murakami, Kazuaki, イノウエ, コウジ, ムラカミ, カズアキ
2000-ARC-140-6
A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size (2000)
Inoue, Koji, Kai, Koji, Murakami, Kazuaki, 井上, 弘士, 甲斐, 康司, 村上, 和彰, ...
This paper proposes an on-chip memory-path architecture employing the dynamically variable line-size (D-VLS) cache for high performance and low energy consumption. The D-VLS cache exploits the high...
Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems (2000)
Inoue, Koji, Kai, Koji, Murakami, Kazuaki, 井上, 弘士, 甲斐, 康司, 村上, 和彰, ...
Intelligent Memory Systems: Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers
Hashimoto, Koji, Yamasaki, Masaya, Tomita, Hiroto, Metsugi, Katsuhiko, Murakami, Kazuaki, 橋本, 浩二, ...
3rd International Conference on SCI-based Technology and Research (SCI-Europe 2000) : August 29th-30th, 2000 : Germany
「プログラム実行の局所性」の活用法に関する検討 (2000)
林田, 隆則, 村上, 和彰, Hayashida, Takanori, Murakami, Kazuaki, ハヤシダ, タカノリ, ムラカミ, カズアキ
CPSY2000-48
制御依存およびデータ依存制約を緩和することの効果 : Lam and Wilsonの評価結果の改訂 (2000)
目次, 勝彦, 村上, 和彰, Metsugi, Katsuhiko, Murakami, Kazuaki, メツギ, カツヒコ, ムラカミ, カズアキ
CPSY2000-49
Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs (2000)
Inoue, Koji, Kai, Koji, Murakami, Kazuaki, 井上, 弘士, 甲斐, 康司, 村上, 和彰, ...
This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache(D-VLS cache)." The D-VLS cache can optimize its line-size...
動的可変ラインサイズ・キャッシュ・アーキテクチャとその性能およびオンチップDRAMの消費エネルギーに関する評価 (2000)
井上, 弘士, 甲斐, 康司, 村上, 和彰, Inoue, Koji, Kai, Koji, Murakami, Kazuaki, ...
我々は, DRAM/ロジック混載LSI向けキャッシュ・アーキテクチャとして、動的可変ラインサイズ・キャッシュ(D-VLSキャッシュ)を提案している.D-...
Inoue, Koji, Kai, Koji, Murakami, Kazuaki, 井上, 弘士, 甲斐, 康司, 村上, 和彰, ...
International Symposium on Low-Power and High-Speed Chips (COOL Chips III) : April 24-25, 2000 : Tokyo
High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs (1999)
Koji Inoue, Koji Kaiy, Kazuaki Murakami
Merged DRAM/logic LSIs could provide high on-chip memory bandwidth by interconnecting logic portions and DRAM with wider on-chip buses. For merged DRAM/logic LSIs with the memory hierarchy including...
Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption (1999)
Koji Inoue, Tohru Ishihara, Kazuaki Murakami
This paper proposes a new approach using way prediction for achieving high performance and low energy consumption of set-associative caches. By accessing only a single cache way predicted, instead of...
Koji Inoue, Koji Kaiy, Kazuaki Murakami
Merged DRAM/logic LSIs could provide high on-chip memory bandwidth by interconnecting logic portions and DRAM with wider on-chip buses. For merged DRAM/logic LSIs with the memory hierarchy including...
On-chip Memorypath Architectures for Parallel Processing (1997)
Hiroshi Miyajima, Koji Inoue, Koji Kaiy, Kazuaki Murakami
This paper discusses on-chip memorypath architectures of merged DRAM/logic LSIs. Merged DRAM/logic LSIs have many benefits; higher memory bandwidth, lower memory latency, lower system power, and so...
Hyperscalar Processor Architecture (in Japanese (1994)
Kazuaki Murakami, Hiroshi Miyajima, Yasuhiko Saitoh, Tetsuo Hironaka, Satoru Shirakawa
This paper describes a novel processor architecture, called hyperscalar processor architecture, which encompasses the advantages of superscalar, VLIW, and vector processor architectures and exculdes...
Hyperscalar Processor Architecture (in Japanese (1994)
Kazuaki Murakami, Hiroshi Miyajima, Yasuhiko Saitoh, Tetsuo Hironaka, Satoru Shirakawa
This paper describes a novel processor architecture, called hyperscalar processor architecture, which encompasses the advantages of superscalar, VLIW, and vector processor architectures and exculdes...
Hyperscalar Processor Architecture (in Japanese (1994)
Kazuaki Murakami, Hiroshi Miyajima, Yasuhiko Saitoh, Tetsuo Hironaka, Satoru Shirakawa
This paper describes a novel processor architecture, called hyperscalar processor architecture, which encompasses the advantages of superscalar, VLIW, and vector processor architectures and exculdes...
Merged Dram/logic Lsis, Koji Inoue, Koji Kai, Kazuaki Murakami
er proposesa novelca he aI hitecture suitatu for merged DRAM/logic LS s, which isca595 "dyna+I cayn vaH[5CI line-sizeca he (D-VLS cache). " The D-VLSca he ca optimize its line-size...