High-Throughput Decoder for Low-Density Parity-Check Code (2009)
Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto
Abstract — We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regular LDPC...
An Area-Efficient GF(2 m) MSD Multiplier based on an MSB Multiplier for Elliptic Curve LSI (2008)
Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Abstract: In this paper, we propose an MSD (most significant digit) multiplier based on an MSB (most significant bit) multiplier over GF(2 m). The proposed multiplier is based on connecting D (digit...
Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique (2008)
SHIMIZU, Kazunori, TOGAWA, Nozomu, IKENAGA, Takeshi, GOTO, Satoshi
Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder...
A 41 mW VGA@30 fps Quadtree Video Encoder for Video Surveillance Systems (2008)
LIU, Qin, HIRATSUKA, Seiichiro, SHIMIZU, Kazunori, USHIKI, Shinsuke, GOTO, Satoshi, IKENAGA, Takeshi
Video surveillance systems have a huge market, as indicated by the number of installed cameras, particularly for low-power systems. In this paper, we propose a low-power quadtree video encoder for...
Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms (2007)
WANG, Qi, SHIMIZU, Kazunori, IKENAGA, Takeshi, GOTO, Satoshi
In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with...
Cooperated Ieee, Fukuoka Chapter, Yao-wen Chang, Charlie Chen, Eui-young Chung, Maziar Goudarzi, ...
Aim of the Workshop
Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule (2006)
SHIMIZU, Kazunori, ISHIKAWA, Tatsuyuki, TOGAWA, Nozomu, IKENAGA, Takeshi, GOTO, Satoshi
In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning...
Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule (2006)
SHIMIZU, Kazunori, ISHIKAWA, Tatsuyuki, TOGAWA, Nozomu, IKENAGA, Takeshi, GOTO, Satoshi
In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations...
Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving (2005)
SHIMIZU, Kazunori, TOGAWA, Nozomu, IKENAGA, Takeshi, GOTO, Satoshi
This paper proposes a reconfigurable adaptive FEC system based on Reed-Solomon (RS) code with interleaving. In adaptive FEC schemes, error correction capability t is changed dynamically according to...
A Reconfigurable Adaptive FEC System for Reliable Wireless Communications (2004)
Shimizu, Kazunori, Togawa, Nozomu, Ikenaga, Takeshi, Yanagisawa, Masao, Goto, Satoshi, Ohtsuki, Tatsuo
A Reconfigurable Adaptive FEC System for Reliable Wireless Communications (2004)
Shimizu, Kazunori, Togawa, Nozomu, Ikenaga, Takeshi, Yanagisawa, Masao, Goto, Satoshi, Ohtsuki, Tatsuo
Shimizu, Kazunori, Hayashi, Shuhei, Kako, Takeshi, Suzuki, Maiko, Tsukagoshi, Norihiko, Doukyu, Noriyuki, ...
Gene expression profiles were collected from Escherichia coli strains (OST3410, TK33, and TK31) before and after exposure to organic solvents, and the six genes that showed higher gene expression...
Shimizu, Kazunori, Hayashi, Shuhei, Kako, Takeshi, Suzuki, Maiko, Tsukagoshi, Norihiko, Doukyu, Noriyuki, ...
Gene expression profiles were collected from Escherichia coli strains (OST3410, TK33, and TK31) before and after exposure to organic solvents, and the six genes that showed higher gene expression...