TOGAWA, Nozomu, TACHIKAKE, Koichi, MIYAOKA, Yuichiro, YANAGISAWA, Masao, OHTSUKI, Tatsuo
This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm...
Instruction Set and Functional Unit Synthesis for SIMD Processor Cores (2004)
Togawa, Nozomu, Tachikake, Koichi, Miyaoka, Yuichiro, Yanagisawa, Masao, Ohtsuki, Tatsuo