This proposal describes the research project which concentrates on task scheduling for distributed heterogeneous computer architectures. The main emphasis of the proposed research is on such...
A New Necessary Condition for Shortest Path Routing (2008)
Mats Petter Pettersson, Krzysztof Kuchcinski
Abstract. In shortest path routing, traffic is routed along shortest paths defined by link weights. However, not all path systems are feasible in that they can be realized in this way. This is...
HardwareBoftware Partitioning with Iterative Improvement Heuristics (2008)
Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alexa Doboli
The paper presents two heuristics for hardwarelsoftware partitioning of system level
This paper presents a new high-level synthesis (HLS) approach which addresses the problem of synthesis of conditional behaviors. In proposed methodology, the conditional behaviors are represented by...
Abstract. This paper presents an application of finite domain constraint programming methods to digital system synthesis problems. The modeling methods address basic synthesis problems of high-level...
Back-Annotation of VHDL Behavioral Models for Postsynthesis Simulation (2007)
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli
The paper presents an approach to back-annotation of VHDL specifications containing time-constraints, for postsynthesis behavioral simulation. As a distinct feature, the mechanism does not rely on...
Toward Automatic Test Pattern Generation for VHDL Descriptions (2007)
This paper describes an approach for defining a model for the VHDL descriptions which can be used for test generation purpose. The VHDL description can be transformed to this model by semantic...
Two Methods for Synthesizing VHDL Concurrent Processes (2007)
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Marius Minea
This paper presents two methods for high-level synthesis of VHDL specifications containing concurrent processes, that were implemented in the CAMAD high-level synthesis system. Our synthesis subset,...
Specification of Timing Constraints in VHDL for High-Level Synthesis (2007)
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli
This paper deals with the problem of timing constraint specification in VHDL for high-level synthesis purposes. We first discuss some possible approaches and define the basic requirements for a...
Automatic Diagnosis of VLSI Digital Circuits Using Algorithmic Debugging (2007)
Krzysztof Kuchcinski, Wlodzimierz Drabent, Jan Maluszynski
. This paper discusses application of the technique of algorithmic debugging, originating from logic programming, to automatic diagnosis of VLSI digital circuits. In particular, the main aim of the...
An Integrated Design Methodology for Digital Systems (2007)
Krzysztof Kuchcinski, Zebo Peng
: Today's digital systems usually consist of interacting hardware and software components of high complexity. Design of such systems requires support of efficient design methodologies and...
Multifrequency Test And Diagnosis Of Analog (2007)
Circuits Using Constraint, Ana Fuentes Martínez, Krzysztof Kuchcinski
Analog circuits are often specified using non-linear equations, which are difficult to analyze. Therefore, test generation and diagnosis are problematic issues in practice. In this paper we propose a...
Partial Task Assignment of Task Graphs under Heterogeneous Resource Constraints (2003)
Radoslaw Szymanek, Krzysztof Kuchcinski
This paper presents a novel partial assignment technique (PAT) that decides which tasks should be assigned to the same resource without explicitly defining assignment of these tasks to a particular...
Integrating a computational model and a run time system for image processing on a uav (2002)
Per Andersson, Krzysztof Kuchcinski
Recently substantial research has been devoted to
Kuchcinski, Krzysztof, Wolinski, Christophe
Abstract not available
A Constructive Algorithm for Memory-Aware Task Assignment and Scheduling (2001)
Szymanek, Radoslaw, Kuchcinski, Krzysztof
Abstract not available
LEneS: Task-Scheduling for Low-Energy Systems Using Variable Voltage Processors (2001)
Gruian, Flavian, Kuchcinski, Krzysztof
Abstract not available
Digital Systems Design Using Constraint Logic Programming (2000)
Radoslaw Szymanek, Flavius Gruian, Krzysztof Kuchcinski
Abstract. This paper presents an application of finite domain constraint logic programming methods to digital system synthesis problems. The modeling methods address basic synthesis problems of...
Performance oriented partitioning for time-multiplexed FPGA’s (2000)
Per Andersson, Krzysztof Kuchcinski
Time-multiplexing is a promising method to reduce the cost of FPGA based systems. It means execution of logic in consecutive steps with reconfiguration taking place between these steps. The use of...
Design space exploration in system level synthesis under memory constraints (1999)
Radoslaw Szymanek, Krzysztof Kuchcinski
This paper addresses the problem of component selection, task assignment and task scheduling for distributed embedded computer systems. Such systems have a large number of constraints of different...
System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search (1997)
Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alexa Doboli
This paper presents two heuristics for automatic hardware/software partitioning of system level specifications. Partitioning is performed at the granularity of blocks, loops, subprograms, and...
Post-Synthesis Back-Annotation of Timing Information in Behavioral VHDL (1995)
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli
This paper presents an approach to back-annotation of timing information in behavioral VHDL descriptions. In our approach, a behavioral VHDL description specifies the functionality and timing...
Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alexa Doboli
This paper presents two heuristics for automatic hardware/software partitioning of system level specifications. Partitioning is performed at the granularity of loops, subprograms, and processes with...
Post-Synthesis Back-Annotation of Timing Information in (1995)
Behavioral Vhdl Petru, Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli
This paper presents an approach to back-annotation of timing information in behavioral VHDL descriptions. In our approach, a behavioral VHDL description specifies the functionality and timing...
An Algorithm for Partitioning of Application Specific Systems (1993)
Zebo Peng, Krzysztof Kuchcinski
This paper presents a simulated-annealing based algorithm to partition an application specific system into a set of modules. The role of partitioning is to discover the structure implicit in the...
Compiling vhdl into a high-level synthesis design representation (1992)
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Marius Minea
The paper discusses the problem of extending the use of VHDL to the field of hardware synthesis.The main difficulty lies in the fact that the semantics of standard VHDL is defined strictly in terms...
A Unified Approach to Evaluation and Design of Hardware/Software Systems (1991)
Zebo Peng, Johan Fagerström, Krzysztof Kuchcinski
This paper presents a unified approach to the design of application-specific systems which consist of both hardware and software components. Our approach is based on the development of an formal...