SET Fault Injection Methods in Analog Circuits: Case Study (2008)
A. Ammari, L. Anghel, R. Leveugle
Abstract — Fault injection techniques have been proposed recently to early analyze the dependability characteristics of analog circuits. The aim of this paper is to compare SPICE level and high...
TOOLS AND METHODOLOGY DEVELOPMENT FOR PULSED LASER FAULT INJECTION IN SRAM-BASED FPGAS (2008)
V. Pouget, A. Douin, D. Lewis, P. Fouillat, G. Foucard, P. Peronnard, ...
Abstract: This paper presents the development of a set of tools and the associated methodology for performing pulsed laser fault injection experiments in SRAM-based FPGAs. The new platform allows...
Conception Robuste dans les Technologies CMOS et post-CMOS (2007)
Les technologies de silicium sapprochent de leurs limites physiques en termes de réduction des tailles des transistors, et de la tension dalimentation, daugmentation de la vitesse de...
Conception Robuste dans les Technologies CMOS et post-CMOS (2007)
Les technologies de silicium s’approchent de leurs limites physiques en termes de réduction des tailles des transistors, et de la tension d’alimentation, d’augmentation de la vitesse de...
Conception Robuste dans les Technologies CMOS et post-CMOS (2007)
Les technologies de silicium sapprochent de leurs limites physiques en termes de réduction des tailles des transistors, et de la tension dalimentation, daugmentation de la vitesse de...
Conception Robuste dans les Technologies CMOS et post-CMOS (2007)
Les technologies de silicium sapprochent de leurs limites physiques en termes de réduction des tailles des transistors, et de la tension dalimentation, daugmentation de la vitesse de...
Les limites technologiques du silicium et tolérance aux fautes (2006)
Les technologies de silicium s'approchent de leurs limites physiques en termes de réduction de tailles des transistors, et de la tension d'alimentation (VDD), d'augmentation de la vitesse de...
Issues related to on-line testing are increasingly important in modern electronics systems. In particular, the huge complexity of electronic systems has seen reliability needs growing up in various...
Lazzari, C., Anghel, L., Reis, R.
Soft error rates induced by cosmic radiation become unacceptable in future very deep sub-micron technologies. Many hardening techniques at different abstraction levels have been proposed to cope with...
Evaluation of SET and SEU effects at multiple abstraction levels (2005)
Anghel, L., Leveugle, R., Vanhauwaert, P.
This paper reviews the main approaches used to evaluate the effect of single event transients and single event upsets in digital circuits described at different abstraction levels. The two fault...
Simulation and mitigation of single event effects (2005)
This special session includes a presentation on nuclear codes used to determine a data-base of secondary ion species and their energies produced by the neutron-silicon and neutron-oxygen...
Evaluation of memory built-in self repair techniques for high defect density technologies (2004)
Anghel, L., Achouri, N., Nicolaidis, M.
Memory built in self repair (BISR) is gaining importance since several years. New fault tolerance approaches are mandatory to cope with increasing defect levels affecting memories produced with...
Simulating single event transients in VDSM ICs for ground level radiation (2004)
Alexandrescu, D., Anghel, L., Nicolaidis, M.
This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell....
Coupling Different Methodologies to Validate Obsolete Microprocessors (2004)
Anghel, L., Velazco, R., Sanchez, E., Sonza Reorda, M., Squillero, G.
The actual operating life time for many electronic systems turned out being much longer than originally foreseen, leading to the use of obsolete components in critical projects. To skip...
Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologies (2004)
Anghel, L., Nicolaidis, M., Achouri, N.
Memory Built In Self Repair (BISR) is gaining importance since several years. New fault tolerance approaches are mandatory to cope with increasing defect levels affecting memories produced with...
A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies (2004)
Nicolaidis, M., Achouri, N., Anghel, L.
Memory Built In Self Repair (BISR) is gaining importance since several years. Because defect densities are increasing with submicron scaling, more advanced solutions may be required for memories to...
Simulating single event transients in VDSM ICs for ground level radiation”, JETTA (2004)
Tima Laboratory, D. Alexandrescu, L. Anghel, M. Nicolaidis, Dan Alexandrescu, Lorena Anghel, ...
To be communicated to LATw'2002
A Methodology for Test Replacement Solutions of Obsolete Processors (2003)
Velazco, R., Anghel, L., Saleh, S.
Obsolescence of electronic components is a big concern affecting most electronic equipments involved in safety critical applications (automotive, avionics, airframe, nuclear plants, military...
Memory Built-In Self-Repair for Nanotechnologies (2003)
Nicolaidis, M., Achouri, N., Anghel, L.
This paper presents memory Built-In Self-Repair approaches allowing to achieve high yield for defect densities several orders of magnitude higher than in current technologies. Such repair schemes...
A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities (2003)
Nicolaidis, M., Achouri, N., Anghel, L.
This paper presents the architecture of a new memory Built-In Self-Repair approach targeting memories affected by high defect densities (several orders of magnitude higher than in current...
Preliminary Validation of an Approach Dealing with Processor Obsolescence (2003)
Anghel, L., Velazco, R., Saleh, S., Deswaertes, S., El Moucary, A.
Processor obsolescence is a big concern affecting most equipments involved in safety critical applications (automotive, aerospace, nuclear plants, military applications ). Indeed, such applications...
New methods for evaluating the impact of single event transients in VDSM ICs (2002)
Alexandrescu, D., Anghel, L., Nicolaidis, M.
This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell....
Les limites technologiques du silicium et tolérance aux fautes (2001)
Les technologies de silicium s'approchent de leurs limites physiques en termes de réduction de tailles des transistors, et de la tension d'alimentation (VDD), d'augmentation de la vitesse de...
Les limites technologiques du silicium et tolérance aux fautes (2001)
Les technologies de silicium s'approchent de leurs limites physiques en termes de réduction de tailles des transistors, et de la tension d'alimentation (VDD), d'augmentation de la vitesse de...
Les limites technologiques du silicium et tolérance aux fautes (2001)
Les technologies de silicium s'approchent de leurs limites physiques en termes de réduction de tailles des transistors, et de la tension d'alimentation (VDD), d'augmentation de la vitesse de...
Les limites technologiques du silicium et tolérance aux fautes (2001)
Les technologies de silicium s'approchent de leurs limites physiques en termes de réduction de tailles des transistors, et de la tension d'alimentation (VDD), d'augmentation de la vitesse de...
Les limites technologiques du silicium et tolérance aux fautes (2001)
Les technologies de silicium s'approchent de leurs limites physiques en termes de réduction de tailles des transistors, et de la tension d'alimentation (VDD), d'augmentation de la vitesse de...
Cost reduction and evaluation of a temporary faults detecting technique (2000)
IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise,...
Self-checking circuits versus realistic faults in very deep submicron (2000)
Anghel, L., Nicolaidis, M., Alzaher-Noufal, I.
IC technologies are approaching the ultimate limits of silicon in terms of device size, power supply levels and speed. By approaching these limits, circuits are becoming increasingly sensitive to...
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy (2000)
Anghel, L., Alexandrescu, D., Nicolaidis, M.
IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise,...
Concurrent checking for VLSI (1999)
This paper presents various concurrent checking techniques for VLSI, including self-checking circuits and concurrent checking techniques for temporary faults based on time redundancy. It cautions...
Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS (1999)
Calin, T., Anghel, L., Nicolaidis, M.
This paper describes results on Built-In Current Sensors destined to overcome the limitations of IDDQ testing in deep submicron circuits. The problems of performance penalty, test accuracy and test...
Low frequency noise in silicon carbide Schottky diodes (1997)
Anghel, L., Ouisse, T., Billon, T., Lassagne, P., Jaussaud, C.
The excess low frequency noise of silicon carbide Schottky diodes has been systematically measured on n-type SiC devices with Ti gates. The noise results have been related to general properties such...
Experimental investigation of noise sources in silicon carbide Schottky barriers (1996)
Anghel, L., Ouisse, T., Billon, T., Lassagne, P., Jaussaud, C.
The excess low frequency noise of silicon carbide Schottky diodes has been systematically measured on n-type silicon carbide devices with Ti gate. The noise results have been related to general...
Method to increase the switching speed of MOS transistors by dynamic bias of the bulk (1995)
Mitu, F., Brezeanu, G., Dilimot, G., Anghel, L., Enache, I.
The paper presents a new method to increase the switching speed of MOS circuits by the decrease of the turn-off time of the MOS transistor. Using the bulk electrode as the second command gate the...
Fire safety of tall building (1981)
Bibliography: leaves 166-169. Includes diagrams, plans.