Adaptive Set Pinning: Managing Shared Caches in Chip Multiprocessors ∗ (2009)
Shekhar Srikantaiah, Mahmut Kandemir, Mary Jane Irwin
As part of the trend towards Chip Multiprocessors (CMPs) for the next leap in computing performance, many architectures have explored sharing the last level of cache among different processors for...
Special Issue Short Papers Transistor Sizing for Low Power CMOS Circuits (2009)
Manjit Borah, Robert Michael Owens, Mary Jane Irwin
Abstruct- A direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is pre-sented. In contrast to the existing assumption that the power...
A Helper Thread Based EDP Reduction Scheme for Adapting Application Execution in CMPs (2009)
Yang Ding, Mahmut K, Padma Raghavan, Mary Jane Irwin
In parallel to the changes in both the architecture domain – the move toward chip multiprocessors (CMPs) – and the application domain – the move toward increasingly data-intensive workloads –...
� � Chandrakasan et.al. – Design of High Performance Microprocessor Circuits (2009)
Mary Jane Irwin, Mahmut Kandemir, Vijaykrishnan Narayanan, Instructors Irwin
� � Class notes � � Class will run to 12:45 to compensate for cancelled classes; PDG Short Course Vijaykrishnan Narayanan 2 © PSU
Mary Jane Irwin, Mahmut Kandemir, Vijaykrishnan Narayanan, Yuan Xie
� E.g., transistor sizing, DVS, clock gating
Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors ∗ (2009)
Ozcan Ozturk, Mahmut K, Mary Jane Irwin
This paper proposes an integer linear programming (ILP) solution to the combined problem of memory hierarchy design and data allocation in the context of embedded chip multiprocessors. The proposed...
Embedded Systems Design M•CORE Architecture (2008)
● provides adequate functionality and performance ● lowers power ● maximizes code density ● provides efficient interrupt processing for real-time I/O
CSE 597C. Energy-Efficient Design Energy Analysis.2 (2008)
Mary Jane Irwin, Mahmut K, Vijaykrishnan Narayanan
P = C L V DD 2 f0→1 + t scV DD I peak f 0→1+ V DD I leakage Dynamic term (~90 % today and decreasing relatively) f 0→1 = P 0→1 * f clock Short-circuit term (~8 % today and decreasing...
Mary Jane Irwin, Mahmut Kandemir, Vijaykrishnan Narayanan, Yuan Xie, Instructors Irwin
� Introduce sources of power consumption � Learn different techniques to reduce power consumption � Understand different noise sources � Identify interactions between power optimizations and...
● Introduction and motivation ● Processor core power reduction techniques ● Memory system power reduction techniques
Lin Li, N. Vijaykrishnan, Mahmut K, Mary Jane Irwin
Crosstalk between wires, caused by increased capacitive coupling, is considered one of the major factors that affect the performance of interconnects such as buses. The datadependent nature of...
Leakage-Aware Interconnect for On-Chip Network (2008)
Yuh-fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin
On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes...
ABSTRACT Optimizing Sensor Movement Planning for Energy Efficiency ∗ (2008)
Guiling Wang, Mary Jane Irwin, Piotr Berman, Haoying Fu, Tom La Porta
Conserving the energy for motion is an important yet notwell-addressed problem in mobile sensor networks. In this paper, we study the problem of optimizing sensor movement for energy efficiency. We...
A Compiler-Based Approach for Dynamically Managing Scratch-Pad Memories in Embedded Systems (2008)
Mahmut K, Associate Member, J. Ramanujam, Mary Jane Irwin, N. Vijaykrishnan, Associate Member, ...
Abstract—Optimizations aimed at improving the efficiency of on-chip memories in embedded systems are extremely important. Using a suitable combination of program transformations and memory design...
Embedded Systems Design (2008)
Mary Jane Irwin, Mary Jane Irwin, Vijay Narayanan, Mahmut Kandemir, Anand Sivasubramanian, Guohong Cao
● Sophisticated functionality » complex algorithms » user interfaces, complex I/O » safety and reliability issues ● Multiples, real-time constraints » real time, multi-rate ● Costs and...
ESSES 2003 Design of Reliable Power-Efficient Power Efficient Systems (2008)
Pdg Shortcourse, Mary Jane Irwin, Mahmut Kandemir, Vijaykrishnan Narayanan, Yuan Xie, Reliable Reliable, ...
area speed/area speed power speed/power low power 1970’s 1980’s 1990’s 2000’s Page 1 © PSU speed/power/reliability speed/power / reliability reliable ultra-low ultra low power
Conjugate Gradient Sparse Solvers: Performance-Power Characteristics ∗ (2008)
Korad Malkowski, Ingyu Lee, Padma Raghavan, Mary Jane Irwin
We characterize the performance and power attributes of the conjugate gradient (CG) sparse solver which is widely used in scientific applications. We use cycle-accurate simulations with SimpleScalar...
Heterogeneous Integration of Nanowires for Chemical Sensor Arrays NSF NIRT Grant 0303981 (2008)
Pis Thomas, E. Mallouk, Mary Jane Irwin, Theresa S. Mayer, Stephane Evoy, ...
Nanoscale chemical sensors offer great promise for use in cross-reactive arrays because of their inherent high sensitivity, low power requirements, and potential for massive redundancy. Electronic...
Leakage-Aware Interconnect for On-Chip Network (2008)
Yuh-fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin
On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes...
Chapter 10 COMPILER OPTIMIZATIONS FOR LOW POWER SYSTEMS (2008)
Mahmut K, N. Vijaykrishnan, Mary Jane Irwin
Abstract Most current compiler optimizations focus on improving execution time. With the increasingly widespread use of embedded systems, however, power/energy consumption is also becoming an...
Abstract Validation of an Architectural Level Power Analysis Technique (2008)
Rita Yu, Chen Robert, M. Owens, Mary Jane Irwin, Raminder S. Bajway
This paper presents a technique used to dopower analysis of a real processor at the architectural level. The target processor integrates a 16-bit DSP anda32-bit RISC on a single chip. Our power...
Abstract Validation of an Architectural Level Power Analysis Technique (2007)
Rita Yu, Chen Robert, M. Owens, Mary Jane Irwin, Raminder S. Bajway
This paper presents a technique used to dopower analysis of a real processor at the architectural level. The target processor integrates a 16-bit DSP anda32-bit RISC on a single chip. Our power...
Benjamin Bishop, Mary Jane Irwin, Thomas P. Kelliher
Abstract- In this paper, we discuss hardware acceleration for real-time physical modeling that would allow for realistic virtual environments. Additionally, we propose algorithms and their...
Design Considerations for Databus Charge Recovery (2007)
Benjamin Bishop, Victor Lyuboslavsky, N. Vijaykrishnan, Mary Jane Irwin
Abstract | The charge recovery databus is a scheme which reduces energy consumption through the application of adiabatic circuit techniques. Previous work [2] gives a solid theoretical analysis of...
Lin Li, N. Vijaykrishnan, Mahmut K, Mary Jane Irwin
With dramatic scaling in feature sizes, noise resilience is becoming one of the most important design parameters, similar to performance and energy efficiency. Noise resilience is particularly...
Impact of Process Scaling on the Efficacy of Leakage Reduction Schemes (2007)
Yuh-fang Tsai, David Duarte, N. Vijaykrishnan, Mary Jane Irwin
The effects of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) are evaluated by determining their limits and...
BB-GC: Basic-Block Level Garbage Collection (2005)
Ozturk, Ozcan, Kandemir, Mahmut, Irwin, Mary Jane
Memory space limitation is a serious problem for many embedded systems from diverse application domains. While circuit/packaging techniques are definitely important to squeeze large quantities of...
Leakage-Aware Interconnect for On-Chip Network (2005)
Tsai, Yuh-Fang, Narayaynan, Vijaykrishnan, Xie, Yuan, Irwin, Mary Jane
On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes...
Leakage-Aware Interconnect for On-Chip Network (2005)
Tsai, Yuh-Fang, Narayaynan, Vijaykrishnan, Xie, Yuan, Irwin, Mary Jane
On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes...
BB-GC: Basic-Block Level Garbage Collection (2005)
Ozturk, Ozcan, Kandemir, Mahmut, Irwin, Mary Jane
Memory space limitation is a serious problem for many embedded systems from diverse application domains. While circuit/packaging techniques are definitely important to squeeze large quantities of...
Ozcan Ozturk, Mahmut K, Mary Jane Irwin
Minimizing the number of off-chip memory references is very important in chip multiprocessors from both the performance and power perspectives. To achieve this the distance between successive reuses...
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty (2005)
Yuh-fang Tsai, N. Vijaykrishnan, Yuan Xie, Mary Jane Irwin
One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage reduction techniques...
Three-dimensional cache design exploration using 3dcacti (2005)
Yuh-fang Tsai, Yuan Xie, N. Vijaykrishnan, Mary Jane Irwin
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a way to mitigate the...
Analysis of error recovery schemes for networks on chips (2005)
Srinivasan Murali, Theocharis Theocharides, Luca Benini, Giovanni De Micheli, N. Vijaykrishnan, Mary Jane Irwin
Network on Chip (NoC) interconnects based on packet-switched communication have been recently proposed for providing scalable and reliable on-chip communication. Due to shrinking transistor sizes and...
Three-dimensional cache design exploration using 3dcacti (2005)
Yuh-fang Tsai, Yuan Xie, N. Vijaykrishnan, Mary Jane Irwin
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a way to mitigate the...
Soft Error and Energy Consumption Interactions: A Data Cache Perspective (2004)
Lin Li, Vijay Degalahal, N. Vijaykrishnan, Mahmut K, Mary Jane Irwin
Energy-efficiency and reliability are two major design constraints influencing next generation system designs. In this work, we focus on the interaction between power consumption and reliability...
ChipPower: An architecture-level leakage simulator (2004)
Yuh-fang Tsai, Ananth Hegde Ankadi, N. Vijaykrishnan, Mary Jane Irwin, Theo Theocharides
Leakage power is projected to be one of the major challenges in future technology generations. The temperature profile, process variation, and transistor count all have strong impact on the leakage...
N. Vijaykrishnan, Mahmut K, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, David Duarte, ...
Abstract—With the emergence of a plethora of embedded and portable applications, energy dissipation has joined throughput, VLSI layout area, and accuracy/precision as a major design constraint....
Mary Jane Irwin, Mahmut Kandemir, Vijaykrishnan Narayanan, Yuan Xie, Variable V T
�Lecture 4 (today and …): �Datapath dynamic power optimizations �Class cancelled on September 18 (Thursday) �In-class project discussion September 23 �Cache modifications for reliability...
Interplay of Energy and Performance for Disk Arrays Running Transaction Processing Workloads (2003)
Sudhanva Gurumurthi, Jianyong Zhang, Anand Sivasubramaniam, Mahmut Kandemir, Hubertus Franke, N. Vijaykrishnan, ...
The growth of business enterprises and the emergence of the Internet as a medium for data processing has led to a proliferation of applications that are server-centric. The power dissipation of such...
Managing leakage energy in cache hierarchies (2003)
Lin Li, Ismail Kadayif, Yuh-fang Tsai, N. Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin, ...
Energy management is important for a spectrum of systems ranging from high-performance architectures to low-end mobile and embedded devices. With the increasing number of transistors, smaller feature...
Interplay of Energy and Performance for Disk Arrays Running Transaction Processing Workloads (2003)
Sudhanva Gurumurthi, Jianyong Zhang, Anand Sivasubramaniam, Mahmut Kandemir, Hubertus Franke, N. Vijaykrishnan, ...
The growth of business enterprises and the emergence of the Internet as a medium for data processing has led to a proliferation of applications that are server-centric. The power dissipation of such...
Managing Leakage Energy in Cache Hierarchies (2003)
Lin Li, Ismail Kadayif, Yuh-fang Tsai, N. Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin, ...
Energy management is important for a spectrum of systems ranging from high-performance architectures to low-end mobile and embedded devices. With the increasing number of transistors, smaller feature...
N. Vijaykrishnan, Mahmut Kandemir, Mahmut K, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, ...
With the emergence of a plethora of embedded and portable applications, energy dissipation has joined throughput, VLSI layout area, and accuracy/precision as a major design constraint. Thus,...
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors (2003)
Lin Li, N. Vijaykrishnan, Mahmut Kandemir, Mahmut K, Mary Jane Irwin, Ismail Kadayif
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for building complex single...
Partitioned Instruction Cache Architecture for Energy Efficiency (2002)
Soontae Kim, N. Vijaykrishnan, Mahmut Kandemir, Anand Sivasub, Mary Jane Irwin
The demand for high-performance architectures and powerful battery-operated mobile devices has accentuated the need for low power systems. In many media and embedded applications, the memory system...
Impact of technology scaling in the clock system power (2002)
David Duarte, Vijaykrishnan Narayanan, Mary Jane Irwin
The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is briefly reviewed...
Evaluating run-time techniques for leakage power reduction (2002)
David Duarte, Yuh-fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimizations and are applied at...
Impact of technology scaling in the clock system power (2002)
David Duarte, Vijaykrishnan Narayanan, Mary Jane Irwin
The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is briefly reviewed...
A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations (2002)
David E. Duarte, N. Vijaykrishnan, Mary Jane Irwin
The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume at least a quarter of the power budget of existing...
Call For Participation, Vivek De, Mary Jane Irwin
The 9th IEEE International Conference on Electronics, Circuits, and Systems – ICECS 2002 will be held in Dubrovnik, Croatia on September 15– 18, 2002. The conference will be an inspiring forum...
M Agazine, Call For Participation, Vivek De, Mary Jane Irwin
The 9th IEEE International Conference on Electronics, Circuits, and Systems – ICECS 2002 will be held in Dubrovnik, Croatia on September 15– 18, 2002. The conference will be an inspiring forum...
Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries (2001)
Sudhanva Gurumurthi, Ning An, Anand Sivasubramaniam, N. Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin
A seamless infrastructure for information access and data processing is the backbone for the successful development and deployment of the envisioned ubiquitous/mobile applications of the near future....
Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries (2001)
Sudhanva Gurumurthi, N. Vijaykrishnan, Ning An, Mahmut Kandemir, Anand Sivasubramaniam, Mary Jane Irwin
A seamless infrastructure for information access and data processing is the backbone for the successful development and deployment of the envisioned ubiquitous/mobile applications of the near future....
Energy issues in multimedia systems (1999)
Mary Jane Irwin, Vijaykrishnan Narayanan
Abstract- This paper presents possible optimizations to reduce the energy budget for SoC designs that will be used in next generation multimedia systems. Since future multimedia systems will include...
A detailed analysis of mediabench (1999)
Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin
Abstract- In this paper, we present a detailed analysis of the MediaBench benchmark suite. MediaBench consists of a number of popular embedded applications for communications and multimedia....
The Design of a Register Renaming Unit (1999)
Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin
Register renaming is often used to improve performance in many high-ILP processors. However, there is a lack of publications regarding register renaming hardware design. This paper presents a...
Aggressive dynamic execution of multimedia kernel traces (1998)
Benjamin Bishop, Robert Owens, Mary Jane Irwin
There has been relatively little analytical work on processor optimizations for multimedia applications. With the introduction of MMX by Intel, it is clear that this is an area of increasing...
Re-Evaluating MPEG Motion Compensation Search Criteria (1998)
Benjamin Bishop, Thomas P. Kelliher, Robert M. Owens, Mary Jane Irwin
As processors evolve from simple scalar machines to more advanced designs using dynamic instruction scheduling, speed critical algorithms should be re-examined to ensure that the optimal strategy is...
Aggressive Dynamic Execution of Multimedia Kernel Traces (1998)
Benjamin Bishop Robert, Robert Owens, Mary Jane Irwin
There has been relatively little analytical work on processor optimizations for multimedia applications. With the introduction of MMX by Intel, it is clear that this is an area of increasing...
Aggressive Dynamic Execution of Decoded Traces (1997)
Benjamin Bishop, Robert Owens, Mary Jane Irwin
Abstract- In this paper, we consider the increased performance that can be obtained by using in concert, three previously proposed (and in two cases used in commercial systems) ideas. These ideas are...
Aggressive Dynamic Execution of Decoded Traces (1997)
Benjamin Bishop, Thomas P. Kelliher, Robert M. Owens, Mary Jane Irwin
Abstract. In this paper, we consider the increased performance that can be obtained by using, in concert, three previously proposed enhancements. These enhancements are aggressive dynamic (run time)...
An Extended Addressing Mode for Low Power (1997)
Atul Kalambur, Mary Jane Irwin
This paper demonstrates the feasibility of a registermemory addressing mode in microprocessors targeted for low power applications. Using a high level power profiling tool that performs software...
Energy-performance trade-offs for spatial access methods on memory-resident data (1996)
Ning An, Sudhanva Gurumurthi, Anand Sivasubramaniam, N. Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin
The proliferation of mobile and pervasive computing devices has brought energy constraints into the limelight, together with performance considerations. Energy-conscious design is important at all...
Energy-performance trade-offs for spatial access methods on memory-resident data (1996)
Ning An, Sudhanva Gurumurthi, Narayanan Vijaykrishnan, Mahmut K, Mary Jane Irwin
Abstract. The proliferation of mobile and pervasive computing devices has brought energy constraints into the limelight. Energy-conscious design is important at all levels of system architecture, and...
Benjamin R. Liblit, William H. Winsborough, Barry Pangrle, Mary Jane Irwin
Single assignment languages, such as Prolog or Standard ML, endure considerable inef-ficiency to support their declarative semantics. Lacking destructive assignment, programs written in these...
An arithmetic unit for on-line computation--[microform] /--by Mary Jane Irwin. (1977)
Thesis (Ph. D.)--University of Illinois at Urbana-Champaign, 1977.
A four function calculator /--by Mary Jane Irwin. (1975)
Thesis (M.S.)--Memphis State University.