NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication (2009)
Tushar Krishna, Amit Kumar, Patrick Chiang, Mattan Erez, Li-shiuan Peh
As processor core counts increase, networks-on-chip (NoCs) are becoming an increasingly popular interconnection fabric due to their ability to supply high bandwidth. However, NoCs need to deliver...
Abstract Speculation Techniques for Improving Load Related Instruction Scheduling (2009)
Adi Yoaz, Mattan Erez, Ronny Ronen, Stephan Jourdan
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for dispatching instructions...
Abstract Sequoia: Programming the Memory Hierarchy (2008)
Kayvon Fatahalian, Timothy J. Knight, Mike Houston, Mattan Erez, Daniel Reiter, Horn Larkhoon, ...
We present Sequoia, a programming language designed to facilitate the development of memory hierarchy aware parallel programs that remain portable across modern machines featuring different memory...
My research focus in computer architecture is on the critical aspects of locality, parallelism, and bandwidth. This work encompasses improving the cooperation between the hardware, compiler, and...
Abstract Sequoia: Programming the Memory Hierarchy (2008)
Kayvon Fatahalian, Timothy J. Knight, Mike Houston, Mattan Erez, Daniel Reiter, Horn Larkhoon, ...
We present Sequoia, a programming language designed to facilitate the development of memory hierarchy aware parallel programs that remain portable across modern machines featuring different memory...
as the Cell Broadband Engine, Stanford’s Merrimac, and Clear- (2008)
Mattan Erez, Jung Ho Ahn, Jayanth Gummaraju, Mendel Rosenblum, William J. Dally
The recent emergence of compute-intensive stream processors such
Architectural Support for the Stream Execution Model on General-Purpose Processors (2008)
Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mendel Rosenblum, William J. Dally
There has recently been much interest in stream processing, both in industry (e.g., Cell, NVIDIA G80, ATI R580) and academia (e.g., Stanford Merrimac, MIT RAW), with stream programs becoming...
Abstract Speculation Techniques for Improving Load Related Instruction Scheduling (2007)
Adi Yoaz, Mattan Erez, Ronny Ronen, Stephan Jourdan
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for dispatching instructions...
Compilation for explicitly managed memory hierarchies (2007)
Timothy J. Knight, Ji Young, Park Manman, Ren Mike Houston, Mattan Erez, Kayvon Fatahalian, ...
We present a compiler for machines with an explicitly managed memory hierarchy and suggest that a primary role of any compiler for such architectures is to manipulate and schedule a hierarchy of bulk...
Fault tolerance techniques for the merrimac streaming supercomputer (2005)
Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally
As device scales shrink, higher transistor counts are available while soft-errors, even in logic, become a major concern. A new class of architectures, such as Merrimac and the IBM Cell, take...
Fault tolerance techniques for the merrimac streaming supercomputer (2005)
Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally
As device scales shrink, higher transistor counts are available while soft-errors, even in logic, become a major concern. A new class of architectures, such as Merrimac and the IBM Cell, take...
Analysis and performance results of a molecular modeling application on Merrimac (2004)
Mattan Erez, Jung Ho, Ahn Ankit, Garg William, J. Dally, Eric Darve
The Merrimac supercomputer uses stream processors and a highradix network to achieve high performance at low cost and low power. The stream architecture matches the capabilities of modern...
Stream Register Files with Indexed Access (2004)
Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William J. Dally
Many current programmable architectures designed to exploit data parallelism require computation to be structured to operate on sequentially accessed vectors or streams of data. Applications with...
Merrimac: Supercomputing with Streams (2003)
William Dally Patrick, Patrick Hanrahan, Mattan Erez, Timothy J. Knight, François Labonté, Jung-ho Ahn, ...
Merrimac uses stream architecture and advanced interconnection networks to give an order of magnitude more performance per unit cost than cluster-based scientific computers built from the same...
EE482C Project Proposal Brook Compilation (2002)
Jayanth Gummaraju, Ahbishek Das, Mattan Erez
In this project we will develop a basic compiler for Brook. Our aim is to provide the infrastructure for compiling Brook down from the meta-compilation level to the hardware. Our initial hardware...
Stephan Jourdan, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen
This paper describes a new instruction-supply mechanism, called the eXtended Block Cache (XBC). The goal of the XBC is to improve on the Trace Cache (TC) hit rate, while providing the same bandwidth....
Increasing the Instruction-Level Parallelism through Data-Flow Manipulation (2000)
Stephan Jourdan, Adi Yoaz, Mattan Erez
In recent years several techniques for exceeding the program's data-flow constraints have been proposed. These include value prediction, instruction reuse, and dependency redirection. In this...
Stephan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen
This paper describes a new instruction-supply mechanism, called the eXtended Block Cache (XBC). The goal of the XBC is to improve on the Trace Cache (TC) hit rate, while providing the same bandwidth....
Mattan Erez, Brian Towles, Dean Liu, Shuaib Arshad
The majority of modern superscalar processors use Reduced Instruction Set Computer (RISC) type instruction sets. However, their hardware design is no longer aligned with the RISC philosophy and is...
Speculation Techniques for Improving Load Related Instruction Scheduling (1999)
Adi Yoaz, Mattan Erez, Ronny Ronen, Stephan Jourdan
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for dispatching instructions...