The Discovery of a Massive Cluster of Red Supergiants with GLIMPSE (2009)
Alexander, Michael J., Kobulnicky, Henry A., Clemens, Dan P., Jameson, Katherine, Pinnick, April, Pavel, Michael
We report the discovery of a previously unknown massive Galactic star cluster at l=29.22, b=-0.20. Identified visually in mid-IR images from the Spitzer GLIMPSE survey, the cluster contains at least...
New Graph Arborescence and Steiner Constructions for High-Performance FPGA Routing (2007)
Michael J. Alexander, Gabriel Robins
The flexibility and reusability of field-programmable gate arrays (FPGAs) enable significant speed and cost savings in the VLSI design/validation/simulation cycle. However, this is achieved at a...
Memory Bandwidth Optimizations for Wide-Bus Machines (2007)
Michael J. Alex, Michael J. Alexander, Postal Address, Professor Jack, W. Davidson, Michael A. Alexander, ...
One of the critical problems facing designers of high performance processors is the disparity between processor speed and memory speed. This has occurred because innovation and technological...
Placement and Routing for Performance-Oriented FPGA Layout (1998)
Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a...
Power Optimization for FPGA Look-Up Tables (1997)
We explore a new method for reducing power consump-tion/dissipation for FPGAs which is complementary to existing FPGA technology-mapping power-reduction techniques (e.g.,
Placement and Routing for Three-Dimensional FPGAs (1996)
Michael J. Alexander, James P. Cohoon, Jared L. Colflesh, John Karro, Edward L. Peters, Gabriel Robins
We explore physical layout for a three-dimensional (3D) FPGA architecture. For placement, we introduce a topdown partitioning technique based on rectilinear Steiner trees; we then employ a one-step...
New Performance-Driven FPGA Routing Algorithms (1996)
Michael J. Alexander, Gabriel Robins
Motivated by the goal of increasing the performance of FPGA-based designs, we propose effective Steiner and arborescence FPGA routing algorithms. Our graphbased Steiner tree constructions have...
New Performance-Driven FPGA Routing Algorithms (1996)
Michael J. Alexander, Gabriel Robins
Motivated by the goal of increasing the performance of FPGA-based designs, we propose new Steiner and arborescence FPGA routing algorithms. Our Steiner tree constructions significantly outperform the...
Performance-Oriented Placement and Routing for Field-Programmable Gate Arrays (1995)
Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a...
Three-Dimensional Field-Programmable Gate Arrays (1995)
Michael J. Alexander, James P. Cohoon, Jared L. Colflesh, John Karro, Gabriel Robins
Motivated by improving FPGA performance, we propose a new three-dimensional (3D) FPGA architecture, along with a fabrication methodology. We analyze the expected manufacturing yield, and raise...
An Architecture-Independent Unified Approach to FPGA Routing (1993)
Michael J. Alexander, Gabriel Robins
Field-programmable gate arrays (FPGAs) are an inexpensive and flexible "low risk" design alternative to custom integrated circuits. While FPGA partitioning and technology mapping have been...
Memory Bandwidth Optimizations for Wide-Bus Machines (1992)
Michael J. Alexander, Michael J. Alexander, Postal Address, Professor Jack, Jack W. Davidson, Michael A. Alexander, ...
One of the critical problems facing designers of high performance processors is the disparity between processor speed and memory speed. This has occurred because innovation and technological...
The evolving keyboard style of Charles Ives--[microform] /--by Michael John Alexander. (1984)
Thesis (Ph. D.)--University of Keele, 1984.
Placement and Routing for Performance-Oriented FPGA Layout
Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a...