Scientific Commons: Nozomu Togawa

A Hardware/Software Cosynthesis System for CAM Processors (2008)

Abstract — Content addressable memory (CAM) is one of the functional memories which realize wordparallel equivalence search. Since a CAM unit is generally used in a particular application program,...

An Area-Efficient GF(2 m) MSD Multiplier based on an MSB Multiplier for Elliptic Curve LSI (2008)

Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Abstract: In this paper, we propose an MSD (most significant digit) multiplier based on an MSB (most significant bit) multiplier over GF(2 m). The proposed multiplier is based on connecting D (digit...

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique (2008)

SHIMIZU, Kazunori, TOGAWA, Nozomu, IKENAGA, Takeshi, GOTO, Satoshi

Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder...

A Secure Test Technique for Pipelined Advanced Encryption Standard (2008)

SHI, Youhua, TOGAWA, Nozomu, YANAGISAWA, Masao, OHTSUKI, Tatsuo

In this paper, we presented a Design-for-Secure-Test (DFST) technique for pipelined AES to guarantee both the security and the test quality during testing. Unlike previous works, the proposed method...

A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss (2008)

SHI, Youhua, TOGAWA, Nozomu, YANAGISAWA, Masao, OHTSUKI, Tatsuo

This paper presents a unified test compression technique for scan stimulus and unknown masking data with seamless integration of test generation, test compression and all unknown response masking for...

An Interface-Circuit Synthesis Method with Configurable Processor Core in IP-Based SoC Designs (2006)

Kohara, Shunitsu, Tomono, Naoki, Uchida, Jumpei, Miyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, ...

FCSCAN: An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction (2006)

Shi, Youhua, Togawa, Nozomu, Kimura, Shinji, Yanagisawa, Masao, Ohtsuki, Tatsuo

A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (2006)

Jumpei Uchida †a, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

SUMMARY Elliptic curve cryptosystems are expected to be a next standard of public-key cryptosystems. A security level of elliptic curve cryptosystems depends on a difficulty of a discrete logarithm...

FCSCAN: An efficient multiscan-based test compression technique for test cost reduction (2006)

Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki

Abstract — This paper proposes a new multiscan-based test input data compression technique by employing a Fan-out Compression Scan Architecture (FCSCAN) for test cost reduction. The basic idea of...

A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier (2006)

UCHIDA, Jumpei, TOGAWA, Nozomu, YANAGISAWA, Masao, OHTSUKI, Tatsuo

Elliptic curve cryptosystems are expected to be a next standard of public-key cryptosystems. A security level of elliptic curve cryptosystems depends on a difficulty of a discrete logarithm problem...

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule (2006)

SHIMIZU, Kazunori, ISHIKAWA, Tatsuyuki, TOGAWA, Nozomu, IKENAGA, Takeshi, GOTO, Satoshi

In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning...

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule (2006)

SHIMIZU, Kazunori, ISHIKAWA, Tatsuyuki, TOGAWA, Nozomu, IKENAGA, Takeshi, GOTO, Satoshi

In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations...

Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains (2006)

SHI, Youhua, TOGAWA, Nozomu, KIMURA, Shinji, YANAGISAWA, Masao, OHTSUKI, Tatsuo

This paper presents a test input data compression technique, Selective Low-Care Coding (SLC), which can be used to significantly reduce input test data volume as well as the external test channel...

A Processor Core Synthesis System in IP-based SoC Design (2005)

Tomono, Naoki, Kohara, Shuitsu, Uchida, Jumpei, Miyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, ...

A Processor Core Synthesis System in IP-based SoC Design (2005)

Tomono, Naoki, Kohara, Shuitsu, Uchida, Jumpei, Miyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, ...

Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis (2005)

KAWAZU, Hideki, UCHIDA, Jumpei, MIYAOKA, Yuichiro, TOGAWA, Nozomu, YANAGISAWA, Masao, OHTSUKI, Tatsuo

A b-bit SIMD functional unit has n k-bit sub-functional units in itself, where b = k × n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor...

A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition (2005)

TOGAWA, Nozomu, TACHIKAKE, Koichi, MIYAOKA, Yuichiro, YANAGISAWA, Masao, OHTSUKI, Tatsuo

This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm...

Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving (2005)

SHIMIZU, Kazunori, TOGAWA, Nozomu, IKENAGA, Takeshi, GOTO, Satoshi

This paper proposes a reconfigurable adaptive FEC system based on Reed-Solomon (RS) code with interleaving. In adaptive FEC schemes, error correction capability t is changed dynamically according to...

A Reconfigurable Adaptive FEC System for Reliable Wireless Communications (2004)

Shimizu, Kazunori, Togawa, Nozomu, Ikenaga, Takeshi, Yanagisawa, Masao, Goto, Satoshi, Ohtsuki, Tatsuo

Experimental Evaluation of High-Level Energy Optimization Based on Thread Partitioning (2004)

Uchida, Jumpei, Mkiyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo

A Reconfigurable Adaptive FEC System for Reliable Wireless Communications (2004)

Shimizu, Kazunori, Togawa, Nozomu, Ikenaga, Takeshi, Yanagisawa, Masao, Goto, Satoshi, Ohtsuki, Tatsuo

Experimental Evaluation of High-Level Energy Optimization Based on Thread Partitioning (2004)

Uchida, Junpei, Mkiyaoka, Yuichiro, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo

Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test (2004)

Shi, Youhua, Kimura, Shinji, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo

Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test (2004)

Shi, Youhua, Kimura, Shinji, Togawa, Nozomu, Yanagisawa, Masao, Ohtsuki, Tatsuo