Programmable Gate Arrays, Paul S. Graham
Bioinformatics refers to the analysis and the management of biological information. The term computational biology is more often used to address physical and mathematical simulations of biological...
Date Brad, L. Hutchings, Date James, K. Archibald, Date Leroy Bearnson, Date Doran Wilde, ...
of a dissertation submitted by
RECENT RESEARCH AND WORK EXPERIENCE (2007)
• Developed several debugging aids for FPGA-based systems (readback for debugging, design-level scan, bitstreammodifiable embedded logic analyzers, etc.) and aided in the development of JHDL •...
Predicting On-Orbit Static Single Event Upset Rates in Xilinx Virtex FPGAs (2006)
Sponsorship: Department of Energy, Los Alamos National Laboratory. This document describes the methodology used to predict single-event upset rates for Xilinx Virtex FPGAs based on the CREME96 orbit...
Predicting On-Orbit Static Single Event Upset Rates in Xilinx Virtex FPGAs (2006)
Sponsorship: Department of Energy, Los Alamos National Laboratory. This document describes the methodology used to predict single-event upset rates for Xilinx Virtex FPGAs based on the CREME96 orbit...
Predicting On-Orbit Static Single Event Upset Rates in Xilinx Virtex FPGAs (2006)
Sponsorship: Department of Energy, Los Alamos National Laboratory. This document describes the methodology used to predict single-event upset rates for Xilinx Virtex FPGAs based on the CREME96 orbit...
Reconfigurable Computing - Accelerating Computation with Field-Programmable Gate Arrays (2005)
Gokhale, Maya, Graham, Paul S.
This volume is unique: the first comprehensive exposition of the exciting new field of Reconfigurable Computing with FPGAs. By mapping algorithms directly into programmable logic, FPGA accelerators...
Evaluation of Power Costs in Applying TMR to FPGA Designs (2004)
Rollins, Nathaniel; Wirthlin, Michael J., Graham, Paul S.
Sponsorship: Los Alamos National Laboratory. Triple modular redundancy (TMR) is a technique commonly used to mitigate against design failures caused by single event upsets (SEUs). The SEU immunity...
Evaluation of Power Costs in Applying TMR to FPGA Designs (2004)
Sponsorship: Los Alamos National Laboratory. Triple modular redundancy (TMR) is a technique commonly used to mitigate against design failures caused by single event upsets (SEUs). The SEU immunity...
Evaluation of Power Costs in Applying TMR to FPGA Designs (2004)
Sponsorship: Los Alamos National Laboratory. Triple modular redundancy (TMR) is a technique commonly used to mitigate against design failures caused by single event upsets (SEUs). The SEU immunity...
Logical hardware debuggers for fpga-based systems (2001)
Date Brad, L. Hutchings, Date James, K. Archibald, Date Leroy Bearnson, Date Doran Wilde, ...
of a dissertation submitted by
Logical hardware debuggers for fpga-based systems (2001)
Date Brad, L. Hutchings, Date James, K. Archibald, Douglas M. Chabries, ...
of a thesis submitted by
Logical hardware debuggers for fpga-based systems (2001)
Date Brad, L. Hutchings, Date James, K. Archibald, Date Leroy, W. Bearnson, ...
of a dissertation submitted by
Logical hardware debuggers for FPGA-based systems / (2001)
Thesis (Ph. D.)--Brigham Young University, Department of Electrical and Computer Engineering, 2001.
This thesis presents Splash 2 hardware and HP PA-RISC software implementations of a genetic algorithm for symmetric traveling salesman problems, providing an analysis and comparison of the...
This thesis presents Splash 2 hardware and HP PA-RISC software implementations of a genetic algorithm for symmetric traveling salesman problems, providing an analysis and comparison of the...
Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering.