R. Rooyackers

pMOSFET with 200% mobility enhancement induced by multiple stressors (2006)

Nouri, F, Thirupapuliyur, S, Verheyen, P, Moroz, V, ...

Recessed Si0.8Ge0.2 source/drain (S/D) and a compressive contact etch-stop layer have been successfully integrated resulting in nearly 200% improvement in hole mobility. This is the largest reported...

Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors (2003)

Jurczak, M, Grau, L, Linten, D, Augendre, E, De Potter, M, ...

It has been known that using selective epitaxial growth (SEG) silicon, to elevate source/drain regions, is beneficial to digital CMOS by reducing the junction leakage. In addition, this architecture...

Impact of thermal budget on junction leakage in a 0.18 and 0.13 um CMOS technology (2002)

A. Poyai, E. Simoen, C. Claeys, R. Rooyackers, A. Redolfi