Bashir, Sheikh Irfan, Gupta, Rajesh, Khan, Haris Nazir, Ahmed, Rayees, Mohd, Ashraf, Salaria, Abdul Q
Abstract Foot is an unusual site for chondrosarcoma and involvement of phalanges is extremely rare. We report a case of grade 2 chondrosarcoma of proximal phalanx resulting in its fracture along with...
Supersymmetry, Localization and Quantum Entropy Function (2009)
Banerjee, Nabamita, Banerjee, Shamik, Gupta, Rajesh, Mandal, Ipsita, Sen, Ashoke
AdS_2/CFT_1 correspondence leads to a prescription for computing the degeneracy of black hole states in terms of path integral over string fields living on the near horizon geometry of the black...
CATS: Cycle Accurate Transaction-driven Simulation with Multiple Processor Simulators (2009)
Dohyung Kim, Soonhoi Ha, Rajesh Gupta
This paper focuses on enhancing performance of cycle accurate simulation with multiple processor simulators. Simulation performance is determined by how often simulators exchange events with one...
A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems ∗ (2008)
Shivajit Mohapatra, Radu Cornea, Hyunok Oh, Kyoungwoo Lee, Minyoung Kim, Nikil Dutt, ...
The next generation of mobile systems with multimedia processing capabilities and wireless connectivity will be increasingly deployed in highly dynamic and distributed environments for multimedia...
A LE T TH ERE BE •1868• (2008)
Rajesh Gupta, Mani Srivastava, Lig H T
● 35-60 % annual growth in PCS users ● By 2000, one in three phones will be mobile (42 % in US) ● Nordic countries: 10 mobile phones being added for every wireline phone ● Japan: number of...
Energy-Aware Task Scheduling With Task Synchronization for Embedded Real-Time Systems (2008)
Ravindra Jejurikar, Student Member, Rajesh Gupta
Abstract—Slowdown factors determine the extent of slowdown that a computing system can experience based on functional and performance requirements. Dynamic voltage scaling (DVS) of a processor...
IOS Press Formal refinement-checking in a system-level design methodology (2008)
Jean-pierre Talpin, Rajesh Gupta, Paul Le Guernic, Frédéric Doucet
Abstract. Rising complexity and performances, shortening time-to-market demands, stress highlevel embedded system design as a prominent research topic. Ad-hoc design methodologies, that lifts...
Online Strategies for Dynamic Power Management in Systems with Multiple (2008)
Power-saving States, Sandy Irani, Sandeep Shukla, Rajesh Gupta
Online dynamic power management (DPM) strategies refer to strategies that attempt to make power-mode-related decisions based on information available at runtime. In making such decisions, these...
System for Compositional System-on-Chip Design (2008)
Jean-pierre Talpin, Abdoulaye Gamatie, Paul Le, Guernic David Berner, Sandeep K. Shukla, Rajesh Gupta, ...
The design productivity gap has been recognized by the semiconductor industry as one of the major threats to the continued growth of system-on-chips and embedded systems. Ad-hoc system-level design...
Parallel Co-simulation Using Virtual Synchronization with Redundant Host Execution (2008)
Dohyung Kim, Soonhoi Ha, Rajesh Gupta
In traditional parallel co-simulation approaches, the simulation speed is heavily limited by time synchronization overhead between simulators and idle time caused by data dependency. Recent work has...
Sridhar Narayanan, Rajesh Gupta, Melvin Breuer
To reduce the high test time for serial scan designs, the use of multiple scan chains has been proposed. In this paper we consider the problem of optimally constructing multiple scan chains so as to...
Gethin Norman, David Parker, Marta Kwiatkowska, Eep Shukla, Rajesh Gupta
Abstract. Dynamic power management (DPM) refers to the use of runtime strategies in order to achieve a tradeoff between the performance and power consumption of a system and its components. We...
Reactive Framework for Resource Aware Distributed Computing ⋆ (2008)
Rajesh Gupta, R. K. Shyamasundar, In Honour, Jean-louis Lassez
Abstract. Rapid strides in technology have lead to pervasive computing in a spectrum of applications such as crisis management systems, distributed critical systems, medical therapy systems, home...
Parallelizing Compiler Approaches • High-Level Synthesis (2008)
Gaurav Singh, Sumit Gupta, Tensilica Inc, Sandeep Shukla, Rajesh Gupta, A Code
High-Level Synthesis:
Formal Aspects of Computing (2005) Formal Aspects of Computing (2008)
Gethin Norman, David Parker, Marta Kwiatkowska, Eep Shukla, Rajesh Gupta
Using probabilistic model checking for dynamic power management
Optimized Slowdown in Real Time Task Systems (2008)
Ravindra Jejurikar, Student Member, Rajesh Gupta
Abstract—Slowdown factors determine the extent of slowdown a computing system can experience based on functional and performance requirements. Dynamic Voltage Scaling (DVS) of a processor based on...
Energy Efficient Watermarking on Mobile Devices Using Proxy-Based Partitioning (2008)
Arun Kejariwal, Student Member, Sumit Gupta, Ru Nicolau, Nikil D. Dutt, Senior Member, ...
Abstract—Digital watermarking embeds an imperceptible signature or watermark in a digital file containing audio, image, text, or video data. The watermark can be used to authenticate the data file...
Jean-pierre Talpin, Paul Le Guernic, Frédéric Doucet, Rajesh Gupta, P. Le Guernic, ...
Abstract. The productivity gap incurred by the rising complexity of system-on-chip design have necessitated newer design paradigms to be introduced based on system-level design languages. A gating...
ServiceFORGE: A Software Architecture for Power and Quality Aware Services (2008)
Radu Cornea, Nikil Dutt, Rajesh Gupta, Shivajit Mohapatra, Alex Nicolau, Eep Shukla, ...
Abstract. We present a novel power management service in QoS-brokerage architecture that relies on multi-level middleware services to act as brokers in delivering multimedia content in distributed...
Aspects + GAMMA = AspectGAMMA A Formal Framework for Aspect-Oriented Specification (2008)
Mohammad Mousavi, Giovanni Russello, Michel Chaudron, Michel A, Twan Basten, Angelo Corsaro, ...
Abstract. This paper describes an extension to the GAMMA formalism, which we name AspectGAMMA, and we show how non-computational aspects can be expressed separately from the computation in this...
Aspects + GAMMA = AspectGAMMA A Formal Framework for Aspect-Oriented Specification (2008)
Mohammad Mousavi, Giovanni Russello, Michel Chaudron, Michel A. Reniers, Twan Basten, Angelo Corsaro, ...
m.r.mousavi,g.russello,m.r.v.chaudron,
A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems ∗ (2008)
Shivajit Mohapatra, Radu Cornea, Hyunok Oh, Kyoungwoo Lee, Minyoung Kim, Nikil Dutt, ...
The next generation of mobile systems with multimedia processing capabilities and wireless connectivity will be increasingly deployed in highly dynamic and distributed environments for multimedia...
Jean-pierre Talpin, Paul Le Guernic, Eep Kumar, Rajesh Gupta
A compositional behavioral modeling
Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache (2008)
Ru Nicolau, Er Veidembaum, Rajesh Gupta
Abstract—Caches are crucial components of modern processors; they allow high-performance processors to access data fast and, due to their small sizes, they enable low-power processors to save...
Using Aspect-GAMMA in Design and Verification (2008)
Of Embedded Systems, Mohammad Mousavi, Giovanni Russello, Michel Chaudron, Michel Reniers, Twan Basten, ...
Mohammad Mousavi , Giovanni Russello , Michel Chaudron , Michel Reniers , Twan Basten , Angelo Corsaro , Sandeep Shukla , Rajesh Gupta and Douglas C. Schmidt Technische Universiteit Eindhoven (TU/e),...
Software Synthesis using Timed Decision Tables (2007)
Timed Decision Tables (TDTs) have been used earlier for modeling behavioral descriptions, applying presynthesis optimizations for efficient circuit synthesis and HDL restructuring. We describe here...
Interfacing Hardware and Software Using C++ Class Libraries (2007)
Dinesh Ramanathan, Ray Roth, Rajesh Gupta
As chip capacity increases and system-on-a-chip becomes more than just a catch phrase, hardware and system design are being driven in new directions. Systems are designed not just as hardware, but as...
Faster Maximum Mean Cycle Algorithms (2007)
We show that Karp's algorithm processes more vertices and arcs than needed to find the maximum cycle mean of a digraph. This observation motivated us to propose a new scheme, called unfolding,...
Implications of VHDL Timing Models on Simulation and Software Synthesis (2007)
Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee
In this paper, we address the timing semantics of the delay models handled by VHDL. A formal model is used to characterize the runtime work required to resolve multiple assignments to signals for...
Cache With Adaptive Fetch Size 1 (2007)
Weiyu Tang, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
Current cache designs support only one fixed line size. Fixed line size limits cache's ability in spatial/temporal locality utilization. In this report, we present a cache design with multiple...
A Quantative Evaluation of Adaptive Memory Hierarchy (2007)
Memory utilization becomes the performance bottleneck as the gap between CPU speed and memory speed increases rapidly. Architecture engineering is one of the research topics to overcome this problem....
Aspects + GAMMA = AspectGAMMA A Formal Framework for Aspect-Oriented Specification (2007)
Mohammad Mousavi, Giovanni Russello, Michel Chaudron, Michel A, Twan Basten, Angelo Corsaro, ...
Abstract. This paper describes an extension to the GAMMA formalism, which we name AspectGAMMA, and we show how non-computational aspects can be expressed separately from the computation in this...
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alex Nicolau
This paper presents a modular and extensible high-level synthesis research system, called SPARK, that takes a behavioral description in ANSI-C as input and produces synthesizable register-transfer...
1 An Analysis of System Level Power Management Algorithms and Their Eects on Latency (2007)
Dinesh Ramanathan, Sandra Irani, Rajesh Gupta
The problem of power management for an embedded system is to reduce system level power dissipation by shutting o parts of the system when they are not being used and turning them back on when...
3.1 Memory Mapping................................................. 6 (2007)
Manev Luthra, Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alex Nicolau
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) as a pro-grammable co-processor to reduce the computational load on the main processor core. We...
Aspects + GAMMA = AspectGAMMA A Formal Framework for Aspect-Oriented Specification (2007)
Mohammad Mousavi, Giovanni Russello, Michel Chaudron, Michel A, Twan Basten, Angelo Corsaro, ...
Abstract. This paper describes an extension to the GAMMA formalism, which we name AspectGAMMA, and we show how non-computational aspects can be expressed separately from the computation in this...
Mohammad Mousavi, Giovanni Russello, Michel Chaudron, Michel A, Twan Basten, Angelo Corsaro, ...
Abstract. This paper describes an extension to the GAMMA formalism, which we name AspectGAMMA, and we show how non-computational aspects can be expressed separately from the computation in this...
Adaptive Line Size Cache 1 (2007)
Weiyu Tang, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
Current cache designs support only fixed line size. Fixed cache line size limits cache's ability in spatial/temporal locality utilization. In this report, we present a cache design with adaptive...
Conflict miss elimination by time-stride prefetch (2007)
Weiyu Tang, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
Many hardware cache prefetching mechanisms have been proposed to improve cache performance. Most of them rely on spatial locality prediction based on continuously monitoring miss addresses. While...
Interfacing Hardware and Software Using C++ Class Libraries (2007)
Dinesh Ramanathan Ray, Ray Roth, Rajesh Gupta
As chip capacity increases and system-on-a-chip becomes more than just a catch phrase, hardware and system design are being driven in new directions. Systems are designed not just as hardware, but as...
Polychrony for Refinement-Based Design (2007)
Jean-Pierre Talpin, Paul Le Guernic, Sandeep Kumar Shukla, Rajesh Gupta, Frederic Doucet, Virgina Tech
Rising complexities and performances of integrated circuits and systems, shortening time-to-market demands for electronic equipments, growing installed bases of intellectual property, requirements...
Shivajit Mohapatra, Nalini Venkatasubramanian, Nikil Dutt, Cristiano Pereira, Rajesh Gupta
Abstract Optimizing user experience for streaming video applications on handheld devices is a significant research challenge. In this chapter, we propose an integrated end-to-end power management...
Sumit Gupta, Manev Luthra, Nikil Dutt, Rajesh Gupta, Alex Nicolau
Reconfigurable logic such as FPGAs is increasingly being used on system-on-chip (SoC) platforms to provide a flexible, programmable co-processor that augments the core processor. In this paper, we...
A Model-Based Approach to System Specification for Distributed Real-time and Embedded Systems (2007)
Radu Cornea, Shivajit Mohapatra, Nikil Dutt, Rajesh Gupta, Ingolf Kreuger, Alex Nicolau, ...
Distributed, real-time, and embedded (DRE) systems take input from many remote sensors, and provide geographically-dispersed operators with the ability to interact with the collected information and...
IOS Press Formal Refinement Checking in a System-level Design Methodology (2007)
Jean-pierre Talpin, Rajesh Gupta, Paul Le Guernic, Frédéric Doucet
Abstract. Rising complexity, increasing performance requirements, and shortening time-to-market demands necessitate newer design paradigms for embedded system design. Such newer design methodologies...
A Model-Based Approach to System Specification for Distributed Real-time and Embedded Systems (2007)
Radu Cornea, Shivajit Mohapatra, Nikil Dutt, Rajesh Gupta, Ingolf Krueger, Alex Nicolau, ...
Introduction Distributed, real-time, and embedded (DRE) systems take input from many remote sensors, and provide geographically-dispersed operators with the ability to interact with the collected...
Sumit Gupta, Timothy Kam, Michael Kishinevsky, Shai Rotem, Nick Savoiu, Nikil Dutt, ...
High performance microprocessor designs are partially characterized by functional blocks consisting of a large number of operations that are packed into very few cycles (often single-cycle) with...
Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization (2007)
Murali, Srinivasan, Mutapcic, Almir, Atienza, David, Gupta, Rajesh, Boyd, Stephen P., De Micheli, Giovanni
The increasing processing capability of Multi-Processor Systems-on-Chips (MPSoCs) is leading to an increase in chip power dissipation, which in turn leads to significant increase in chip temperature....
Wireless Wakeups Revisited: Energy Management for VoIP over Wi-Fi Smartphones (2007)
Yuvraj Agarwal, Ranveer Ch, Alec Wolman, Paramvir Bahl, Kevin Chin, Rajesh Gupta
IP based telephony is rapidly gaining acceptance over traditional means of voice communication. Wireless LANs are also becoming ubiquitous due to their inherent ease of deployment and decreasing...
Processor Speed Control with Thermal Constraints (2007)
Almir Mutapcic, Stephen Boyd, Srinivasan Murali, David Atienza, Giovanni De Micheli, Rajesh Gupta
We consider the problem of adjusting speeds of multiple computer processors sharing the same thermal environment, such as a chip or multi-chip package. We assume that the speed of processor (and...
Analysis and Design of Transient-Error-Tolerant Nanometer Circuits and Systems (2007)
Chong Zhao, Chung-kuan Cheng, Rajesh Gupta, Bill Lin, Curt Schurgers, Sujit Dey Chair
The dissertation of Chong Zhao is approved, and it is acceptable in quality and form for publication on microfilm:
Wireless Wakeups Revisited: Energy Management for VoIP over Wi-Fi Smartphones (2007)
Yuvraj Agarwal, Ranveer Ch, Alec Wolman, Paramvir Bahl, Kevin Chin, Rajesh Gupta
IP based telephony is rapidly gaining acceptance over traditional means of voice communication. Wireless LANs are also becoming ubiquitous due to their inherent ease of deployment and decreasing...
Optimized slowdown in real-time task systems via geometric programming (2007)
Almir Mutapcic, Srinivasan Murali, Stephen Boyd, Rajesh Gupta, David Atienza, Giovanni De Micheli
savings due to optimal slowdown of periodic tasks in real-time task systems, where tasks have varying power characteristics and task deadlines are less than the periods. The authors presented a...
Temperature-aware processor frequency assignment for MPSoCs using convex optimization (2007)
Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen Boyd, Giovanni De Micheli
The increasing processing capability of Multi-Processor Systemson-Chips (MPSoCs) is leading to an increase in chip power dissipation, which in turn leads to significant increase in chip temperature....
Thelma E. Tupasi, Rajesh Gupta, Ruth B. Orillaza, Nona Rachel Mira, Nellie V. Mangubat, ...
BackgroundMultidrug-resistant tuberculosis (MDR-TB) is an important global health problem, and a control strategy known as DOTS-Plus has existed since 1999. However, evidence regarding the...
Cascaded multilevel control of DSTATCOM using multiband hysteresis modulation (2006)
Ghosh, Arindam, Joshi, Avinash, Gupta, Rajesh
In this paper a cascaded H-bridge inverter topology is used in a distribution static compensator (DSTATCOM). A new multiband hysteresis algorithm is used to control the switches of the cascaded...
Control of 3-level shunt active power filter using harmonic selective controller (2006)
Gupta, Rajesh, Ghosh, Arindam, Joshi, Avinash
In this paper the control of 3-level shunt active power filter is proposed using frequency selective proportional plus multiple resonant controllers. The voltage source converter (VSC) is operated...
Control of 3-level shunt active power filter using harmonic selective controller (2006)
Gupta, Rajesh, Ghosh, Arindam, Joshi, Avinash
In this paper the control of 3-level shunt active power filter is proposed using frequency selective proportional plus multiple resonant controllers. The voltage source converter (VSC) is operated...
Cascaded multilevel control of DSTATCOM using multiband hysteresis modulation (2006)
Ghosh, Arindam, Joshi, Avinash, Gupta, Rajesh
In this paper a cascaded H-bridge inverter topology is used in a distribution static compensator (DSTATCOM). A new multiband hysteresis algorithm is used to control the switches of the cascaded...
Cascaded multilevel control of DSTATCOM using multiband hysteresis modulation (2006)
Ghosh, Arindam, Joshi, Avinash, Gupta, Rajesh
In this paper a cascaded H-bridge inverter topology is used in a distribution static compensator (DSTATCOM). A new multiband hysteresis algorithm is used to control the switches of the cascaded...
Control of 3-level shunt active power filter using harmonic selective controller (2006)
Gupta, Rajesh, Ghosh, Arindam, Joshi, Avinash
In this paper the control of 3-level shunt active power filter is proposed using frequency selective proportional plus multiple resonant controllers. The voltage source converter (VSC) is operated...
Cascaded multilevel control of DSTATCOM using multiband hysteresis modulation (2006)
Ghosh, Arindam, Joshi, Avinash, Gupta, Rajesh
In this paper a cascaded H-bridge inverter topology is used in a distribution static compensator (DSTATCOM). A new multiband hysteresis algorithm is used to control the switches of the cascaded...
Control of 3-level shunt active power filter using harmonic selective controller (2006)
Gupta, Rajesh, Ghosh, Arindam, Joshi, Avinash
In this paper the control of 3-level shunt active power filter is proposed using frequency selective proportional plus multiple resonant controllers. The voltage source converter (VSC) is operated...
Cascaded multilevel control of DSTATCOM using multiband hysteresis modulation (2006)
Ghosh, Arindam, Joshi, Avinash, Gupta, Rajesh
In this paper a cascaded H-bridge inverter topology is used in a distribution static compensator (DSTATCOM). A new multiband hysteresis algorithm is used to control the switches of the cascaded...
Control of 3-level shunt active power filter using harmonic selective controller (2006)
Gupta, Rajesh, Ghosh, Arindam, Joshi, Avinash
In this paper the control of 3-level shunt active power filter is proposed using frequency selective proportional plus multiple resonant controllers. The voltage source converter (VSC) is operated...
Cascaded multilevel control of DSTATCOM using multiband hysteresis modulation (2006)
Ghosh, Arindam, Joshi, Avinash, Gupta, Rajesh
In this paper a cascaded H-bridge inverter topology is used in a distribution static compensator (DSTATCOM). A new multiband hysteresis algorithm is used to control the switches of the cascaded...
Control of 3-level shunt active power filter using harmonic selective controller (2006)
Gupta, Rajesh, Ghosh, Arindam, Joshi, Avinash
In this paper the control of 3-level shunt active power filter is proposed using frequency selective proportional plus multiple resonant controllers. The voltage source converter (VSC) is operated...
Cascaded multilevel control of DSTATCOM using multiband hysteresis modulation (2006)
Ghosh, Arindam, Joshi, Avinash, Gupta, Rajesh
In this paper a cascaded H-bridge inverter topology is used in a distribution static compensator (DSTATCOM). A new multiband hysteresis algorithm is used to control the switches of the cascaded...
Control of 3-level shunt active power filter using harmonic selective controller (2006)
Gupta, Rajesh, Ghosh, Arindam, Joshi, Avinash
In this paper the control of 3-level shunt active power filter is proposed using frequency selective proportional plus multiple resonant controllers. The voltage source converter (VSC) is operated...
Trevor Pering, Yuvraj Agarwal, Rajesh Gupta, Comm Power
CoolSpots enable a wireless mobile device to automatically switch between multiple radio interfaces, such as WiFi and Bluetooth, in order to increase battery lifetime. The main contribution of this...
Trevor Pering, Yuvraj Agarwal, Rajesh Gupta, Comm Power
CoolSpots enable a wireless mobile device to automatically switch between multiple radio interfaces, such as WiFi and Bluetooth, in order to increase battery lifetime. The main contribution of this...
Cascaded multilevel control of DSTATCOM using multiband hysteresis modulation (2006)
Ghosh, Arindam, Joshi, Avinash, Gupta, Rajesh
In this paper a cascaded H-bridge inverter topology is used in a distribution static compensator (DSTATCOM). A new multiband hysteresis algorithm is used to control the switches of the cascaded...
Control of 3-level shunt active power filter using harmonic selective controller (2006)
Gupta, Rajesh, Ghosh, Arindam, Joshi, Avinash
In this paper the control of 3-level shunt active power filter is proposed using frequency selective proportional plus multiple resonant controllers. The voltage source converter (VSC) is operated...
Cascaded multilevel control of DSTATCOM using multiband hysteresis modulation (2006)
Ghosh, Arindam, Joshi, Avinash, Gupta, Rajesh
In this paper a cascaded H-bridge inverter topology is used in a distribution static compensator (DSTATCOM). A new multiband hysteresis algorithm is used to control the switches of the cascaded...
Control of 3-level shunt active power filter using harmonic selective controller (2006)
Gupta, Rajesh, Ghosh, Arindam, Joshi, Avinash
In this paper the control of 3-level shunt active power filter is proposed using frequency selective proportional plus multiple resonant controllers. The voltage source converter (VSC) is operated...
Energy Aware Wireless Systems with Adaptive Power-Fidelity Tradeoffs (2005)
Vijay Raghunathan, Cristiano L. Pereira, Mani B. Srivastava, Rajesh Gupta
Energy aware system operation, and not just low power hardware, is an important requirement for wireless embedded systems. These systems, such as wireless multimedia terminals, wireless sensor nodes,...
Dynamic Phase Analysis for Cycle-Close Trace Generation (2005)
Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh Gupta
For embedded system development, several companies provide cross-platform development tools to aid in debugging, prototyping and optimization of programs. These are full system emulation systems that...
Energy Aware Wireless Systems with Adaptive Power-Fidelity Tradeoffs (2005)
Vijay Raghunathan, Cristiano L. Pereira, Mani B. Srivastava, Rajesh Gupta
Wireless embedded systems, such as multimedia terminals, sensor nodes, etc., combine soft real-time constraints on computation and communication with requirements of long battery lifetime. Energy...
Declarative resource naming for macroprogramming wireless networks of embedded systems (2005)
Chalermek Intanagonwiwat, Rajesh Gupta, Amin Vahdat
Programming Wireless Networks of Embedded Systems (WNES) is notoriously difficult and tedious. To simplify WNES programming, we propose Declarative Resource Naming (DRN) to program WNES as a whole...
Behavioral type inference for compositional system design (2004)
Talpin, Jean-Pierre, Berner, David, Le Guernic, Paul, Gamatié, Abdoulaye, Gupta, Rajesh
The design productivity gap has been recognized by the semiconductor industry as one of the major threats to the continued growth of system-on-chips and embedded systems. Ad-hoc system-level design...
Behavioral type inference for compositional system design (2004)
Talpin, Jean-Pierre, Berner, David, Le Guernic, Paul, Gamatié, Abdoulaye, Gupta, Rajesh, Shukla, Sandeep
The design productivity gap has been recognized by the semiconductor industry as one of the major threats to the continued growth of system-on-chips and embedded systems. Ad-hoc system-level design...
Behavioral type inference for compositional system design (2004)
Talpin, Jean-Pierre, Berner, David, Le Guernic, Paul, Gamatié, Abdoulaye, Gupta, Rajesh, Shukla, Sandeep
The design productivity gap has been recognized by the semiconductor industry as one of the major threats to the continued growth of system-on-chips and embedded systems. Ad-hoc system-level design...
Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis (2004)
Sumit Gupta, Nick Savoiu, Nikil Dutt, Rajesh Gupta, Alex Nicolau
The quality of synthesis results for most high level synthesis approaches is strongly affected by the choice of con-trol flow (through conditions and loops) in the input description. This leads to a...
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alex Nicolau
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. Effective hardware generation...
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures (2004)
Nikhil Bansal, Sumit Gupta, Nikil Dutt, Alex Nicolau, Rajesh Gupta
Several coarse-grain reconfigurable architectures proposed recently consist of a large number of processing elements (PEs) connected in a mesh-like network topology. We study the effects of three...
Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis (2004)
Sumit Gupta, Nick Savoiu, Nikil Dutt, Rajesh Gupta, Alex Nicolau
Abstract—The quality of synthesis results for most high-level synthesis approaches is strongly affected by the choice of control flow (through conditions and loops) in the input description. This...
Systemwide Energy Minimization in Real-Time Embedded Systems (2004)
Ravindra Jejurikar, Rajesh Gupta
Traditionally, dynamic voltage scaling (DVS) techniques have focused on minimizing the processor power consumption as opposed to the entire system energy. However, the slowdown resulting from DVS can...
Procrastination Scheduling in Fixed Priority Real-Time Systems (2004)
Ravindra Jejurikar, Rajesh Gupta
Procrastination scheduling has gained importance for energy efficiency due to the rapid increase in the leakage power consumption. Under procrastination scheduling, task executions are delayed to...
A Behavioral Type Inference System for Compositional System-on-Chip Design (2004)
Jean-Pierre Talpin, David Berner, Sandeep Kumar Shukla, Paul Le Guernic, Abdoulaye Gamatié, Rajesh Gupta, ...
semiconductor industry as one of the major threats to the continued growth of system-on-chips and embedded systems. Ad-hoc system-level design methodologies, that lifts modeling to higher levels of...
Leakage Aware Dynamic Voltage Scaling for Real-Time Embedded Systems (2004)
Ravindra Jejurikar, Cristiano Pereira, Rajesh Gupta
A five-fold increase in leakage current is predicted with each technology generation. While Dynamic Voltage Scaling (DVS) is known to reduce dynamic power consumption, it also causes increased...
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru Nicolau, Ru Nicolau
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a technique called...
Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis (2004)
Sumit Gupta, Nick Savoiu, Student Member, Nikil Dutt, Rajesh Gupta, Senior Member, ...
Abstract — The quality of synthesis results for most high level synthesis approaches is strongly affected by the choice of control flow (through conditions and loops) in the input description. This...
Gupta, Rajesh, Hamdan, Samir M., Dixon, Nicholas E., Sheil, Margaret M., Beck, Jennifer L.
The interactions between the N-terminal domain of the ϵ (ϵ186) and &thetas; subunits of DNA polymerase III of Escherichia coli were investigated using electrospray ionization mass...
Gupta, Rajesh, Hamdan, Samir M., Dixon, Nicholas E., Sheil, Margaret M., Beck, Jennifer L.
The interactions between the N-terminal domain of the ϵ (ϵ186) and &thetas; subunits of DNA polymerase III of Escherichia coli were investigated using electrospray ionization mass...
Gupta, Sumit, Gupta, Rajesh, Dutt, Nikil, Nicolau, A
The quality of high-level synthesis results for designs with complex and nested conditionals and loops can be improved significantly by employing speculative code motions. In this paper, we present...
Electrospray ionisation mass spectrometry of biomolecular complexes (2003)
Electrospray ionisation mass spectrometry (ESI-MS) has been used to study the non-covalent interactions in dsDNA-drug complexes, a protein-protein complex of DNA polymerase III of E. coli and binding...
Electrospray ionisation mass spectrometry of biomolecular complexes (2003)
Electrospray ionisation mass spectrometry (ESI-MS) has been used to study the non-covalent interactions in dsDNA-drug complexes, a protein-protein complex of DNA polymerase III of E. coli and binding...
Electrospray ionisation mass spectrometry of biomolecular complexes (2003)
Typescript. Includes bibliographical references: leaf 210-234.
Electrospray ionisation mass spectrometry of biomolecular complexes (2003)
Electrospray ionisation mass spectrometry (ESI-MS) has been used to study the non-covalent interactions in dsDNA-drug complexes, a protein-protein complex of DNA polymerase III of E. coli and binding...
Electrospray ionisation mass spectrometry of biomolecular complexes (2003)
Electrospray ionisation mass spectrometry (ESI-MS) has been used to study the non-covalent interactions in dsDNA-drug complexes, a protein-protein complex of DNA polymerase III of E. coli and binding...
Electrospray ionisation mass spectrometry of biomolecular complexes (2003)
Electrospray ionisation mass spectrometry (ESI-MS) has been used to study the non-covalent interactions in dsDNA-drug complexes, a protein-protein complex of DNA polymerase III of E. coli and binding...
Electrospray ionisation mass spectrometry of biomolecular complexes (2003)
Electrospray ionisation mass spectrometry (ESI-MS) has been used to study the non-covalent interactions in dsDNA-drug complexes, a protein-protein complex of DNA polymerase III of E. coli and binding...
Electrospray ionisation mass spectrometry of biomolecular complexes (2003)
Electrospray ionisation mass spectrometry (ESI-MS) has been used to study the non-covalent interactions in dsDNA-drug complexes, a protein-protein complex of DNA polymerase III of E. coli and binding...
Electrospray ionisation mass spectrometry of biomolecular complexes (2003)
Electrospray ionisation mass spectrometry (ESI-MS) has been used to study the non-covalent interactions in dsDNA-drug complexes, a protein-protein complex of DNA polymerase III of E. coli and binding...
Electrospray ionisation mass spectrometry of biomolecular complexes (2003)
Electrospray ionisation mass spectrometry (ESI-MS) has been used to study the non-covalent interactions in dsDNA-drug complexes, a protein-protein complex of DNA polymerase III of E. coli and binding...
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alex Nicolau
We present two novel strategies to increase the scope for application of speculative code motions: (1) Adding scheduling steps dynamically during scheduling to conditional branches with fewer...
FORGE: A framework for optimization of distributed embedded systems software (2003)
Radu Cornea, Nikil Dutt, Rajesh Gupta, Ingolf Krueger, Alex Nicolau, Doug Schmidt, ...
New and planned commercial and military distributed, real-time, and embedded (DRE) systems take input from many remote sensors, and provide geographically-dispersed operators with the ability to...
SPARK: A high-level synthesis framework for applying parallelizing compiler transformations (2003)
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alex Nicolau
This paper presents a modular and extensible high-level synthesis research system, called SPARK, that takes a behavioral description in ANSI-C as input and produces synthesizable register-transfer...
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alex Nicolau
We present two novel strategies to increase the scope for application of speculative code motions: (1) Adding scheduling steps dynamically during scheduling to conditional branches with fewer...
Using probabilistic model checking for dynamic power management (2003)
Gethin Norman, David Parker, Marta Kwiatkowska, Eep Shukla, Rajesh Gupta
Energy Efficient Communication for Reliability and Quality Aware Sensor Networks (2003)
Cristiano Pereira, Sumit Gupta, Koushik Niyogi, Iosif Lazaridis, Sharad Mehrotra, Rajesh Gupta
Nodes in a sensor network are typically severely constrained by the amount of power available to them. Furthermore, power consumption by the wireless radio in a sensor node is an order of magnitude...
Interface Synthesis using Memory Mapping for an FPGA Platform (2003)
Manev Luthra, Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alex Nicolau
Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) as a programmable co-processor to reduce the computational load on the main processor core. In this...
Polychrony for Formal Refinement-Checking in a System-Level Design Methodology (2003)
Jean-Pierre Talpin, Paul Le Guernic, Sandeep Kumar Shukla, Rajesh Gupta, Frederic Doucet, Virgina Tech
The productivity gap incurred by the rising complexity of system-on-chip design have necessitated newer design paradigms to be introduced based on systemlevel design languages. A gating factors for...
Using Probabilistic Model Checking for Dynamic Power Management (2003)
Gethin Norman, David Parker, Marta Kwiatkowska, Sandeep Shukla, Rajesh Gupta
We present an approach to deriving stochastic Dynamic Power Management (DPM) strategies that enables us to design both discrete time and continuous time Markov chain based strategies, in a formal and...
FORGE: A Framework for Optimization of Distributed Embedded Systems Software (2003)
Radu Cornea, Nikil Dutt, Rajesh Gupta, Ingolf Krueger, Alex Nicolau, Doug Schmidt, ...
this paper, we describe the architecture of FORGE and specific innovations being pursued. This paper is organized as followed: after a brief overview of the FORGE architecture in Section 2, we...
Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices (2003)
Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta
Digital watermarking is a process that embeds an imperceptible signature or watermark in a digital file containing audio, image, text or video data. The watermark is later used to authenticate the...
Using probabilistic model checking for dynamic power management (2003)
Gethin Norman, David Parker, Marta Kwiatkowska, Eep Shukla, Rajesh Gupta
Abstract. We present an approach to deriving stochastic Dynamic Power Management (DPM) strategies that enables us to design both discrete time and continuous time Markov chain based strategies, in a...
Sandy Irani, Sandeep Shukla, Rajesh Gupta
We present strategies for “online ” dynamic power management(DPM) based on the notion of the competitive ratio that allows us to compare the effectiveness of algorithms against an optimal...
An environment for dynamic component composition for efficient co-design (2002)
Frederic Doucet, Eep Shukla, Rajesh Gupta
This article describes the Balboa component integration environment that is composed of three parts: a script language interpreter, compiled C++ components, and a set of Split-Level Interfaces to...
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis (2002)
Sumit Gupta, Mehrdad Reshadi, Nick Savoiu, Nikil Dutt, Rajesh Gupta, Alex Nicolau
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during scheduling of...
Sumit Gupta, Timothy Kam, Michael Kishinevsky, Shai Rotem, Nick Savoiu, Nikil Dutt, ...
High performance microprocessor designs are partially characterized by functional blocks consisting of a large number of operations that are packed into very few cycles (often single-cycle) with...
Profile-based dynamic voltage scheduling using program checkpoints (2002)
Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil Dutt, Alex Veidenbaum, ...
Dynamic voltage scaling (DVS) is a known effective mechanism for reducing CPU energy consumption without significant performance degradation. While a lot of work has been done on inter-task...
Profile-based dynamic voltage scheduling using program checkpoints (2002)
Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil Dutt, Alex Veidenbaum, ...
Dynamic voltage scaling (DVS) is a known effective mechanism for reducing CPU energy consumption without significant performance degradation. While a lot of work has been done on inter-task...
Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption (2002)
Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh Gupta
In this paper, we present a Branch Target Buffer (BTB) design for energy savings in set-associative instruction caches. We extend the functionality of a BTB by caching way predictions in addition to...
Sandy Irani, Sandeep Shukla, Rajesh Gupta
We present strategies for “online ” dynamic power management(DPM) based on the notion of the competitive ratio that allows us to compare the effectiveness of algorithms against an optimal...
PASA: A software architecture for building power aware embedded systems (2002)
Cristiano Pereira, Rajesh Gupta
We present here a software architecture and an API that enables application developer to explore and build power / performance tradeoffs in the application software and enable the operating system to...
Coordinated parallelizing Compiler optimizations and High-Level Synthesis (2002)
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alex Nicolau
We present a framework for high-level synthesis that enables the designer to explore the best choice of source level and low level parallelizing transformations for improved synthesis. Within this...
An environment for dynamic component composition for efficient co-design (2002)
Frederic Doucet, Eep Shukla, Rajesh Gupta
This article describes the Balboa component integration environment that is composed of three parts: a script language interpreter, compiled C++ components, and a set of Split-Level Interfaces to...
Power savings in embedded processors through decode filter cache (2002)
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau
In embedded processors, instruction fetch and decode can consume more than 40 % of processor power. An instruction filter cache can be placed between the CPU core and the instruction cache to service...
PASA: A software architecture for building power aware embedded systems (2002)
Cristiano Pereira, Vijay Raghunathan, Shalabh Gupta, Rajesh Gupta, Mani Srivastava
As computing moves to battery operated portable systems, the functionality is increasingly implemented in software with an embedded/real-time operating system (RTOS). For such systems, there is a...
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis (2002)
Sumit Gupta, Mehrdad Reshadi, Nick Savoiu, Nikil Dutt, Rajesh Gupta, Alex Nicolau
We introduce a new approach, "Dynamic Common Sub-expression Elimination (CSE)", that dynamically eliminates common sub- expressions based on new opportunities created during...
Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption (2002)
Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh Gupta
In this paper, we present a Branch Target Bu er (BTB) design for energy savings in set-associative instruction caches. We extend the functionality of a BTB by caching way predictions in addition to...
Power savings in embedded processors through decode filter cache (2002)
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau
In embedded processors, instruction fetch and decode can consume more than 40 % of processor power. An instruction filter cache can be placed between the CPU core and the instruction cache to service...
Balboa: A component-based design environment for system models (2002)
Frederic Doucet, Student Member, Eep Shukla, Senior Member, Masato Otsuka, Rajesh Gupta, ...
Abstract—This paper presents the BALBOA component composition framework for system-level architectural design. It has three parts: a loosely-typed component integration language (CIL); a set of C++...
Sumit Gupta, Timothy Kam, Michael Kishinevsky, Shai Rotem, Nick Savoiu, Nikil Dutt, ...
High performance microprocessor designs are partially characterized by functional blocks consisting of a large number of operations that are packed into very few cycles (often single-cycle) with...
Power savings in embedded processors through decode filter cache (2002)
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau
In embedded processors, instruction fetch and decode can consume more than 40 % of processor power. An instruction filter cache can be placed between the CPU core and the instruction cache to service...
Profile-based dynamic voltage scheduling using program checkpoints (2002)
Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil Dutt, Alex Veidenbaum, ...
Dynamic voltage scaling (DVS) is a known effective mechanism for reducing CPU energy consumption without significant performance degradation. While a lot of work has been done on inter-task...
Profile-based dynamic voltage scheduling using program checkpoints (2002)
Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil Dutt, Alex Veidenbaum, ...
Dynamic voltage scaling (DVS) is a known effective mechanism for reducing CPU energy consumption without significant performance degradation. While a lot of work has been done on inter-task...
Dynamic Common Sub-Expression Elimination during (2002)
Sumit Gupta, Mehrdad Reshadi, Nick Savoiu, Nikil Dutt, Rajesh Gupta, ...
We introduce a new approach, "Dynamic Common Sub-expression Elimination (CSE)", that dynamically eliminates common sub- expressions based on new opportunities created during scheduling of...
A Software Architecture for Building Power Aware Real Time (2002)
Operating Systems Cristiano, Cristiano Pereira, Vijay Raghunathan, Shalabh Gupta, Rajesh Gupta, Mani Srivastava
this paper, we present a layered software architecture that enables the application and OS programmers to design energy-efficient applications and RTOS services. The software architecture consists of...
ICS 212 Winter 2002 ICS 212 Winter 2002 Prof Prof. R. Gupta . R. Gupta (2002)
Tasks And Task, Rajesh Gupta, R. Gupta, R. Gupta
es may be given a higher priority than less critical tasks. n Identifying the concurrent tasks early in the design can allow an early performance analysis of the system. l However, concurrent tasking...
Power savings in embedded processors through decode filter cache (2002)
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau
In embedded processors, instruction fetch and decode can consume more than 40 % of processor power. An instruction lter cache can be placed between the CPU core and the instruction cache to service...
Power savings in embedded processors through decode filter cache (2002)
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau
In embedded processors, instruction fetch and decode can consume more than 40 % of processor power. An instruction filter cache can be placed between the CPU core and the instruction cache to service...
Power savings in embedded processors through decode filter cache (2002)
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau
Abstract In embedded processors, instruction fetch and decodecan consume more than 40 % of processor power. An instruction filter cache can be placed between the CPU coreand the instruction cache to...
Energy aware task scheduling with task synchronization for embedded real time systems (2002)
Ravindra Jejurikar, Student Member, Rajesh Gupta
Abstract—Slowdown factors determine the extent of slowdown a computing system can experience based on functional and performance requirements. Dynamic Voltage Scaling (DVS) of a processor based on...
Architectural Adaptation for Power and Performance (2001)
Weiyu Tang, Alexander V. Veidenbaum, Rajesh Gupta
Modern computer architectures represent design tradeoffs involving a large number of variables in a very large design space. Choices related to organization of major system blocks (CPU, cache,...
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau, Alexander V. Veidenbaum
Caches are partitioned into subarrays for optimal timing. In a set-associative cache, if the way holding the data is known before an access, only subarrays for that way need to be accessed. Reduction...
Static analysis of parameterized loop nests for energy efficient use of data caches (2001)
Ru Nicolau, Er Veidenbaum, Rajesh Gupta
Abstract. Caches are an important part of architectural and compiler low-power strategies by reducing memory accesses and energy per access. In this paper, we examine efficient utilization of data...
Static analysis of parameterized loop nests for energy efficient use of data caches (2001)
Ru Nicolau, Er Veidenbaum, Rajesh Gupta
######## # Caches are an important part of architectural and compiler low-power strategies by reducing memory accesses and energy per access. In this paper, we examine ecient utilization of data...
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau
Filter cache has been proposed as an energy saving architectural feature. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruction stream. Energy...
Conditional speculation and its effects on performance and area for high-level synthesis (2001)
Sumit Gupta, Nick Savoiu, Nikil Dutt, Rajesh Gupta, Alex Nicolau
We introduce a code transformation technique, “conditional speculation”, that speculates operations by duplicating them into preceding conditional blocks. This form of speculation belongs to a...
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau, Alexander Veidenbaum
Caches are partitioned into subarrays for optimal timing. In a set-associative cache, if the way holding the data is known before an access, only subarrays for that way need to be accessed. Reduction...
Fetch Size Adaptation vs. Stream Buffer for Media Benchmarks (2001)
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau, Alexander Veidenbaum
In current cache designs, cache size and line size are often fixed and determined by the spatial and temporal locality of benchmarks used to evaluate the targeted processors. Stream buffer and large...
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruction stream. Energy...
Conditional speculation and its effects on performance and area for high-level synthesis (2001)
Sumit Gupta, Nick Savoiu, Nikil Dutt, Rajesh Gupta, Alex Nicolau
We introduce a code transformation technique, “conditional speculation”, that speculates operations by duplicating them into preceding conditional blocks. This form of speculation belongs to a...
Speculation techniques for high level synthesis of control intensive designs (2001)
Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil Dutt, Rajesh Gupta, Alex Nicolau
The quality of synthesis results for most high level synthesis approaches is strongly a ected by the choice of control ow (through conditions and loops) in the input description. In this paper, we...
Speculation techniques for high level synthesis of control intensive designs (2001)
Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil Dutt, Rajesh Gupta, Alex Nicolau
The quality of synthesis results for most high level synthesis approaches is strongly affected by the choice of control flow (through conditions and loops) in the input description. In this paper, we...
Conditional speculation and its effects on performance and area for high-level synthesis (2001)
Sumit Gupta, Nick Savoiu, Nikil Dutt, Rajesh Gupta, Alex Nicolau
We introduce a code transformation technique, "conditional speculation ", that speculates operations by duplicating them into preceding conditional blocks. This form of speculation...
Speculation techniques for high level synthesis of control intensive designs (2001)
Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil Dutt, Rajesh Gupta, Alex Nicolau
Design Automation Conference, June 2001
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau, Alexander V. Veidenbaum
Caches are partitioned into subarrays for optimal timing. In a set-associative cache, if the way holding the data is known before an access, only subarrays for that way need to be accessed. Reduction...
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruction stream. Energy...
Fetch Size Adaptation vs. Stream Buffer for Media Benchmarks (2001)
Weiyu Tang, Rajesh Gupta, Alexander Veidenbaum, Alexandru Nicolau
In current cache designs, cache size and line size are often xed and determined by the spatial and temporal locality of benchmarks used to evaluate the targeted processors. Stream buer and large...
Architectural and compiler strategies for dynamic power management in the copper project (2001)
Ana Azevedo, Radu Cornea, Ilya Issenin, Rajesh Gupta, Nikil Dutt, Alex Nicolau, ...
For a range of embedded system applications in mission critical and energy constrained scenarios it is important to be able to dynamically control power consumption in response to changing power...
The Capability Model for IT-enabled Outsourcing Service Providers Volume I: Overview (2001)
Elaine B. Hyder, Bennet Kumar, Vivek Mahendra, Jane Siegel, Rajesh Gupta, Habeeb Mahaboob, ...
Organizations are increasingly delegating their information technology-intensive business activities to external service providers, taking advantage of the rapid evolution of the global...
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau
Filter cache has been proposed as an energy saving architectural feature. A lter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruction stream. Energy savings...
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau, Alexander Veidenbaum
Caches are partitioned intosubarrays for optimal timing. In a set-associative cache, if the way holding the data is known before anaccess, only subarrays for that way need tobe accessed. Reduction in...
Fetch Size Adaptation vs. Stream Bu er for Media Benchmarks 1 (2001)
Weiyu Tang, Rajesh Gupta, Alexandru Nicolau, Alexander Veidenbaum
In current cache designs, cache size and line size are often xed and determined by the spatial and temporal locality ofbenchmarks used to evaluate the targeted processors. Stream bu er and large...
Speculation techniques for high level synthesis of control intensive designs (2001)
Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil Dutt, Rajesh Gupta, Alex Nicolau
The quality of synthesis results for most high level synthesis approaches is strongly a ected by the choice of control ow (through conditions and loops) in the input description. In this paper, we...
A global strategy for the treatment of drug-resistant tuberculosis / (2000)
Thesis (M.P.H.)--Yale University, 2000.
YAML: a tool for hardware design visualization and capture (2000)
Vivek Sinha, Frederic Doucet, Chuck Siska, Rajesh Gupta, Stan Liao, Abhijit Ghosh
Design visualization is an important part of the system design process. In practice, systems are often visualized using a combination of structural and functional entities. In this paper, we describe...
Microelectronic System-on-Chip modeling using objects and their relationships (2000)
Frederic Doucet, Vivek Sinha, Chuck Siska, Rajesh Gupta
System conceptualization and modeling requires support for both hardware and software components specification, and the ability to do complete system simulation rapidly and accurately. In this paper,...
YAML: a tool for hardware design visualization and capture (2000)
Vivek Sinha, Frederic Doucet, Chuck Siska, Rajesh Gupta, Stan Liao, Abhijit Ghosh
Design visualization is an important part of the system design process. In practice, systems are often visualized using a combination of structural and functional entities. In this paper, we describe...
System level online power management algorithms (2000)
Dinesh Ramanathan, Rajesh Gupta
The problem of power management for an embedded system is to reduce system level power dissipation by shutting off parts of the system when they are not being used and turning them back on when they...
Latency effects of system level power management algorithms (2000)
Dinesh Ramanathan, Sandy Irani, Rajesh Gupta
A power management algorithm for an embedded system reduces system level power dissipation by shutting off parts of the system when they are not being used and turning them back on when they are...
Compiler-directed cache assist adaptivity (2000)
Xiaomei Ji, Dan Nicolaescu, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
The performance of a traditional cache memory hierarchy can be improved by utilizing mechanisms such as a victim cache or a stream buffer (cache assists). The amount of on--chip memory for cache...
Cache with Adaptive Fetch Size (2000)
Weiyu Tang, Weiyu Tang, Er V. Veidenbaum, Er V. Veidenbaum, Ru Nicolau, Ru Nicolau, ...
Current cache designs support only a fixed line size. Fixed cache line size limits cache's ability to utilize spatial/temporal locality. Previously, we proposed an ALS cache, where each...
Compiler-directed cache assist adaptivity (2000)
Xiaomei Ji, Dan Nicolaescu, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
Abstract. The performance of a traditional cache memory hierarchy can be improved by utilizing mechanisms such as a victim cache or a stream buffer (cache assists). The amount of on--chip memory for...
Compiler-directed Cache Line Size Adaptivity (2000)
Dan Nicolaescu, Xiaomei Ji, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
Abstract. The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size that is...
System Level Online Power Management Algorithms (2000)
Dinesh Ramanathan, Rajesh Gupta
The problem of power management for an embedded system is to reduce system level power dissipation by shutting off parts of the system when they are not being used and turning them back on when they...
Analysis of High-level Address Code Transformations for Programmable Processors (2000)
Sumit Gupta, Miguel Miranda, F. Catthoor, R. K. Gupta, Francky Catthoor, Rajesh Gupta
Memory intensive applications require considerable arithmetic for the computation and selection of the different memory access pointers. These memory address calculations often involve complex...
Cache With Adaptive Fetch Size 1 (2000)
Weiyu Tang, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
Current cache designs support only one xed line size. Fixed line size limits cache's ability in spatial/temporal locality utilization. In this report, we present a cache design with multiple...
Compiler-directed Cache Line Size Adaptivity (2000)
Dan Nicolaescu, Xiaomei Ji, Er Veidenbaum, Ru Nicolau, Rajesh Gupta
Abstract. The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size that is xed...
Con ict Miss Elimination by Time-stride Prefetch 1 (2000)
Weiyu Tang, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
Many hardware cache prefetching mechanisms have been proposed to improve cache performance. Most of them rely on spatial locality prediction based oncontinuously monitoring miss addresses. While this...
Compiler-directed cache assist adaptivity (2000)
Xiaomei Ji, Dan Nicolaescu, Er Veidenbaum, Ru Nicolau, Rajesh Gupta
Abstract. The performance of a traditional cache memory hierarchy can be improved by utilizing mechanisms such as a victim cache or a stream bu er (cache assists). The amount of on{chip memory for...
Compiler-directed cache assist adaptivity (2000)
Xiaomei Ji, Dan Nicolaescu, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
The performance of a traditional cache memory hierarchy can be improved by utilizing mechanisms such as a victim cache or a stream bu er (cache assists). The amount of on{ chip memory for cache...
Microelectronic System-on-Chip modeling using objects and their relationships (2000)
Frederic Doucet, Vivek Sinha, Chuck Siska, Rajesh Gupta
System conceptualization and modeling requires support for both hardware and software components speci cation, and the ability to do complete system simulation rapidly and accurately. In this paper,...
Adapting line size cache (1999)
Weiyu Tang, Er V. Veidenbaum, Ru Nicolau, Rajesh Gupta
Current cache design supports only fixed line size. In this report, we propose an adaptive line size cache where line size can dynamically change based on a locality prediction mechanism. Overall...
Adapting Cache Line Size to Application Behavior (1999)
Er V. Veidenbaum, Weiyu Tang, Rajesh Gupta, Ru Nicolau, Xiaomei Ji
A cache line size has a significant effect on miss rate and memory traffic. Today's computers use a fixed line size, typically 32B, which may not be optimal for a given application. Optimal size...
System-on-Chip Modeling Using Objects and Their Relationships (1999)
Frederic Doucet, Vivek Sinha, Chuck Siska, Rajesh Gupta
System conceptualization and modeling requires support for both hardware and software components specification, and the ability to do complete system simulation rapidly and accurately. In this paper,...
SIMPRESS: A Simulator Generation Environment for System-on-Chip Exploration (1999)
Asheesh Khare, Rajesh Gupta, Alexandru Nicolau, Nikil D. Dutt, Committee Chair
of the Thesis SIMPRESS: A Simulator Generation Environment for System-on-Chip Exploration by Asheesh Khare Master of Science in Information and Computer Science University of California, Irvine, 1999...
Unified Modeling Language (UML) (1999)
tion . Hardware is reactive, parallel and timed -- use library support for modeling reactivity, parallelism and timing -- object-orientation is a natural choice for modeling discrete event systems...
Adapting Cache Line Size to Application Behavior (1999)
Er V. Veidenbaum, Weiyu Tang, Rajesh Gupta
Abstract A cache line size has a significant effect on miss rate and memory traffic. Today's computers use a fixed line size, typically 32B, which may not be optimal for a given application....
Adaptive Line Size Cache 1 (1999)
Weiyu Tang, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
Current cache designs supportonly xed line size. Fixed cache line size limits cache's ability in spatial/temporal locality utilization. In this report, we present a cache design with adaptive...
Software Synthesis using Timed Decision Tables (1999)
Timed Decision Tables (TDTs) have been used earlier for modeling behavioral descriptions, applying presynthesis optimizations for e cient circuit synthesis and HDL restructuring. We describe here...
COPPER: Compiler-Controlled On-Demand Approach to Power-Efficient Computing (1998)
Dutt, Nikil, Gupta, Rajesh, Nicolau, Alex, Veidenbaum, Alex
The goal of this research was to build and demonstrate a capability in hardware (processors-memory) and software for management of power resources, and explore its trade-off against speed, accuracy...
High-Level Modeling of Communication in Real-Time Embedded Systems (1998)
Dinesh Ramanathan, Ali Dasdan, Rajesh Gupta
An embedded system continuously interacts with its environment under strict timing constraints. We model an embedded system using a generalized task graph (GTG). Nodes in a GTG represent individual...
A General Approach for Regularity Extraction in Datapath Circuits (1998)
Amit Chowdhary, Sudhakar Kale, Phani Saripella, Naresh Sehgal, Rajesh Gupta
In majority of high-performance custom IC designs, designers take advantage of the high degree of regularity present in circuits to generate e#cientlayouts in terms area and performance as well as to...
High-Level Modeling of Communications in Real-Time Embedded Systems (1998)
Dinesh Ramanathan, Ali Dasdan, Rajesh Gupta
An embedded system continuously interacts with its environment under strict timing constraints. We model an embedded system using a generalized task graph (GTG). Nodes in a GTG represent individual...
System-Level Synthesis Using Evolutionary Algorithms (1998)
Tobias Blickle, Jürgen Teich, J Urgen Teich, Lothar Thiele, Rajesh Gupta
. In this paper, we consider system-level synthesis as the problem of optimally mapping a task-level specification onto a heterogeneous hardware/software architecture. This problem requires (1) the...
Rajesh Satapathy, Rajesh Gupta
The paper presents an analysis of technology trends based on the data available from the recently released National Technology Roadmap for Semiconductors (NTRS 1997). This analysis shows that...
Stan Liao, Steve Tjiang, Rajesh Gupta
Reactivity is one of the key features of hardware description languages. We present an efficient implementation of reactivity in the Scenic framework that allows the system designer to model hardware...
Control Optimizations Using Behavioral Don't Cares (1996)
Optimization of control flow is an important problem in the synthesis of embedded systems. While considerable progress has been made in data-oriented optimizations, control optimization has been...
System-Level Synthesis Using Evolutionary Algorithms (1996)
Tobias Blickle And, Tobias Blickle, J Urgen Teich, Lothar Thiele, Rajesh Gupta
. In this paper, we consider system-level synthesis as the problem of optimally mapping a task-level specification onto a heterogeneous hardware/software architecture. This problem requires (1) the...
Hardware-software Co-synthesis for Digital Systems (1993)
Rajesh Gupta, Giovanni De Micheli
As the complexity of system design increases, use of pre-designed components, such as generalpurpose microprocessors, provides an effective way to reduce the complexity of synthesized hardware. While...
The Programmable Gate Array Data Book (1992)
Dinesh Ramanathan, Ali Dasdan, Rajesh Gupta
Task structuring is the process of determining the individual tasks of a system, leading to the system's description as a task graph. This paper shows that RADHA-RATAN, our rate derivation...
Timing-Driven HW/SW Codesign Based on Task Structuring and Process Timing Simulation (1992)
Dinesh Ramanathan, Ali Dasdan, Rajesh Gupta
Task structuring is the process of determining the individual tasks of a system, leading to the system's description as a task graph. This paper shows that RADHA-RATAN, our rate derivation...
Synthesis of systems containing application-specific as well as reprogrammable components, such as off-the-shelf microprocessors, provides a promising approach to realization of complex systems using...
Transformations for behavioral synthesis /--by Rajesh Gupta. (1991)
Thesis (M.S., Engineering)--University of California, Irvine, 1991.
What happens to patients who leave hospital against medical advice?
Hwang, Stephen W., Li, Jianli, Gupta, Rajesh, Chien, Vince, Martin, Rochelle E.
Transhiatal Esophageal Resection for Corrosive Injury
Gupta, Narendar Mohan, Gupta, Rajesh
Transhiatal esophageal resection was safely used in 49 of 51 patients for corrosive injury without any mortality and low morbidity. Good functional outcome was achieved in all the patients.
Tupasi, Thelma E, Gupta, Rajesh, Quelapio, Ma Imelda D, Orillaza, Ruth B, Mira, Nona Rachel, Mangubat, Nellie V, ...
Evaluation of 117 patients enrolled in a DOTS-Plus pilot project in the Philippines showed that in this setting the strategy is feasible.
Why Should Medical Students Care about Health Policy?
Gupta argues that medicine has become increasingly influenced by political, economic and social policies, and that medical students should become well-versed in these policies.
What happens to patients who leave hospital against medical advice?
Hwang, Stephen W., Li, Jianli, Gupta, Rajesh, Chien, Vince, Martin, Rochelle E.
Transhiatal Esophageal Resection for Corrosive Injury
Gupta, Narendar Mohan, Gupta, Rajesh
Transhiatal esophageal resection was safely used in 49 of 51 patients for corrosive injury without any mortality and low morbidity. Good functional outcome was achieved in all the patients.
Tupasi, Thelma E, Gupta, Rajesh, Quelapio, Ma Imelda D, Orillaza, Ruth B, Mira, Nona Rachel, Mangubat, Nellie V, ...
Evaluation of 117 patients enrolled in a DOTS-Plus pilot project in the Philippines showed that in this setting the strategy is feasible.
Why Should Medical Students Care about Health Policy?
Gupta argues that medicine has become increasingly influenced by political, economic and social policies, and that medical students should become well-versed in these policies.
Gupta, Rajesh, Hamdan, Samir M., Dixon, Nicholas E., Sheil, Margaret M., Beck, Jennifer L.
The interactions between the N-terminal domain of the ɛ (ɛ186) and θ subunits of DNA polymerase III of Escherichia coli were investigated using electrospray ionization mass spectrometry. The...
Analysis of High-level Address Code Transformations for Programmable Processors
Sumit Gupta, Miguel Miranda, Francky Catthoor, Rajesh Gupta
Memory intensive applications require considerable arithmetic for the computation and selection of the different memory access pointers. These memory address calculations often involve complex...
Electrospray ionisation mass spectrometry of biomolecular complexes
Electrospray ionisation mass spectrometry (ESI-MS) has been used to study the non-covalent interactions in dsDNA-drug complexes, a protein-protein complex of DNA polymerase III of E. coli and binding...
Electrospray ionisation mass spectrometry of biomolecular complexes
Electrospray ionisation mass spectrometry (ESI-MS) has been used to study the non-covalent interactions in dsDNA-drug complexes, a protein-protein complex of DNA polymerase III of E. coli and binding...
Electrospray ionisation mass spectrometry of biomolecular complexes
Electrospray ionisation mass spectrometry (ESI-MS) has been used to study the non-covalent interactions in dsDNA-drug complexes, a protein-protein complex of DNA polymerase III of E. coli and binding...
Bashir, Sheikh Irfan, Gupta, Rajesh, Khan, Haris Nazir, Ahmed, Rayees, Mohd, Ashraf, Salaria, Abdul Q
Foot is an unusual site for chondrosarcoma and involvement of phalanges is extremely rare. We report a case of grade 2 chondrosarcoma of proximal phalanx resulting in its fracture along with...
Can an Infectious Disease Genomics Project Predict and Prevent the Next Pandemic?
Gupta, Rajesh, Michalski, Mark H., Rijsberman, Frank R.
Infectious diseases need a globally coordinated genomic-based movement linking sequencing efforts to development of response tools to mitigate the impact of existing and emerging threats.