Abstract Validation of an Architectural Level Power Analysis Technique (2008)
Rita Yu, Chen Robert, M. Owens, Mary Jane Irwin, Raminder S. Bajway
This paper presents a technique used to dopower analysis of a real processor at the architectural level. The target processor integrates a 16-bit DSP anda32-bit RISC on a single chip. Our power...
Abstract Validation of an Architectural Level Power Analysis Technique (2007)
Rita Yu, Chen Robert, M. Owens, Mary Jane Irwin, Raminder S. Bajway
This paper presents a technique used to dopower analysis of a real processor at the architectural level. The target processor integrates a 16-bit DSP anda32-bit RISC on a single chip. Our power...